Abstract: Control circuit and control processing for a memory system having a system data bus coupled to at least one data output latch. The control circuit and process generate a read command (RC) to enable the at least one data output latch to latch data from the system data bus in response to a read clock signal (RCLK). The read command (RC) occurs substantially simultaneous with the instant that a valid data state exists on the system data bus and is developed without directly monitoring the system data bus. Upon detecting the read clock signal (RCLK) a latch enable signal is generated. A valid data signal is next generated independent of the system data bus through the use of a dummy circuit having multiple dummy cells, dummy bitlines and a common dummy bus.