Abstract: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.

Abstract: Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.

Abstract: A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.

Abstract: A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base blocks includes a SRAM cell, such as an eight-transistor (8T) static random access memory (SRAM) cell, and a local evaluation block coupled to the SRAM cell. The SRAM cell includes independent left wordline input and right wordline input. The SRAM cell includes a read wordline connected high, and a true and complement write bitline pair connected low. In the local evaluation circuit, one input of a NAND gate receiving the read bitline input is connected high. A control signal is combined with an inverted feedback signal to start and stop the ring oscillator.

Abstract: A low power level shifter circuit for high performance integrated circuits includes an input inverter operating in a domain of a first voltage supply and receiving an input signal and a design structure on which the subject circuit resides is provided. An output stage operating in a domain of a higher second voltage supply includes a first output inverter connected to the input inverter and a second output inverter connected in series with the first output inverter. The second output inverter provides a level shifted output signal having a voltage level corresponding to the second voltage supply. A series connected finisher transistor and finisher control transistor are connected between the second voltage supply and an input to the first output inverter. The finisher control transistor is activated responsive to the input signal. A path control transistor controls a path between the first voltage supply and the input inverter.

Abstract: A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.

Abstract: A low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a first inverted signal. An output inverter operating in a domain of a second voltage supply coupled to the input inverter and provides an output signal having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second voltage supply is higher than the first voltage supply. A leakage current control circuit includes a finisher transistor connected between the second voltage supply and the input to the output inverter and a path control transistor control a path between the first voltage supply and the input inverter.

Abstract: A method implements static random access memory (SRAM) cell write performance evaluation. A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.

Abstract: A method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation, and a design structure on which the subject circuit resides are provided. ASRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.

Abstract: A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.

Abstract: A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.

Abstract: A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.

Abstract: A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.

Abstract: A low power level shifter circuit for integrated circuits, and a design structure on which the subject circuit resides are provided. The low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a first inverted signal. An output inverter operating in a domain of a second voltage supply coupled to the input inverter and provides an output signal having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second voltage supply is higher than the first voltage supply. A leakage current control circuit includes a finisher transistor connected between the second voltage supply and the input to the output inverter and a path control transistor control a path between the first voltage supply and the input inverter.

Abstract: A low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a first inverted signal. An output inverter operating in a domain of a second voltage supply coupled to the input inverter and provides an output signal having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second voltage supply is higher than the first voltage supply. A leakage current control circuit includes a finisher transistor connected between the second voltage supply and the input to the output inverter and a path control transistor control a path between the first voltage supply and the input inverter.