Abstract: A oscillator having two synchronized oscillator rings is described. Synchronization is accomplished by circuitry connected between the outputs of two aligned stages in coupled oscillator rings, the circuitry being operable to maintain outputs of the stages 180.degree. apart in phase.

Abstract: A frequency doubler is described which is capable of receiving four input signals in quadrature and combining them to produce a pair of antiphase output signals at twice the input frequency.

Abstract: A quadrature oscillator is provided constructed of NOR gates in the manner of a non-linear circuit which is inherently unstable and which cycles sequentially through four distinct states at a rate determined by the constitution of the NOR gates. The quadrature oscillator includes first and second stages that each include first and second NOR gates. The output of the first NOR gate of the first stage is connected as an input to the second NOR gate of each of the first and second stages. The output of the second NOR gate of the first stage is connected as an input to the first NOR gate of each of the first and second stages. The output of the first NOR gate of the second stage is connected as an input to the first NOR gate of the first stage and the second NOR gate of the second stage. The output of the second NOR gate of the second stage is connected as and input to the second NOR gate of the first stage and the first NOR gate of the second stage.

Abstract: A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.

Abstract: A switching circuit for an FET transistor includes a controlled current circuit coupled to the gate of the FET. The input to the controlled current circuit represents a desired rate of change of gate voltage of the FET and is generated by a circuit responsive to the average specific transconductance of two FETs of similar specific transconductance operating at different drain circuit densities.

Abstract: A memory is provided with at least one temporary store and write abort circuitry having a control signal store and gating circuitry responsive to an output from the control signal store. Write circuitry loads data and an associated address in the temporary store during one write cycle and transfer circuitry transfers the data to the associated address during a subsequent write cycle when the write operation is not to be aborted. Read circuitry includes a comparator for comparing a read address with an address in the temporary store and transfer circuitry includes selection circuitry to select an output of data either from the temporary store or the memory dependent on the output of the comparator circuitry, an output from the temporary store being prevented if the control signal store indicates that the write operation is to be aborted.

Abstract: A semiconductor flip-flop memory circuit having a particular spatial format to correct an obvious error.

Abstract: In an NOR decoder for a static random access memory the individual transistor gates (30) are coupled to metallization tracks (31) via polysilicon contact islands (33). The gates of selected transistors are divided into two portions (20a, 20b) disposed on diametrically opposite sides of the corresponding islands (33). This arrangement allows a closer spacing of the tracks (31) than is achieved in conventional layouts.

Abstract: The NOR decoders of a static random access memory are divided into two or more sets only one of which is powered up at any one time. This significantly reduces the power dissipation of the memory and allows the device to be operational under high access speed conditions. In a preferred arrangement each decoding node is clamped to a voltage level significantly lower than the circuit supply voltage. This provides an increase in operating speed by reducing the deselection time.

Abstract: The cells of a static random access memory have a diagonal of `dog leg` structural layout. This permits the use of straight word lines of low impedance and hence of low time constant. Advantageously the work lines are of polysilicon thus permitting a compact design.

Abstract: An energy efficient output circuit for a static random access memory includes a pair of output transistors each driven by a bootstrapped driver stage. This requires less current than conventional amplifier chain.

Abstract: A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.