Abstract: A process for the manufacture of a gallium rich gallium nitride film is described. The process comprises (a) preparing a reaction mixture containing a gallium species and a nitrogen species, the gallium species and the nitrogen species being selected such that, when they react with each other, gallium nitride is formed; and (b) growing the gallium rich gallium nitride film from the reaction mixture, by allowing the gallium species to react with the nitrogen species and to deposit gallium nitride on a substrate selected from the group consisting of silicon, glass, sapphire, quartz and crystalline materials having a lattice constant closely matched to gallium nitride, including zinc oxide, optionally with a zinc oxide buffer layer, at a temperature of from about 480° C. to about 900 ° C. and in the presence of a gaseous environment in which the partial pressure of oxygen is less than 10?4 Torr, wherein the ratio of gallium atoms to nitrogen atoms in the gallium rich gallium nitride film is from 1.01 to 1.20.

Abstract: A process for the manufacture of a gallium rich gallium nitride film is described. The process comprises (a) preparing a reaction mixture containing a gallium species and a nitrogen species, the gallium species and the nitrogen species being selected such that, when they react with each other, gallium nitride is formed; and (b) growing the gallium rich gallium nitride film from the reaction mixture, by allowing the gallium species to react with the nitrogen species and to deposit gallium nitride on a substrate selected from the group consisting of silicon, glass, sapphire, quartz and crystalline materials having a lattice constant closely matched to gallium nitride, including zinc oxide, optionally with a zinc oxide buffer layer, at a temperature of from about 480° C. to about 900° C. and in the presence of a gaseous environment in which the partial pressure of oxygen is less than 10?4 Torr, wherein the ratio of gallium atoms to nitrogen atoms in the gallium rich gallium nitride film is from 1.01 to 1.20.

Abstract: A line scanner comprising an array of CMOS pairs having a common resistive gate. The gate provides a potential gradient along the array in response to a potential difference across its ends, so that the CMOS pairs can receive a gating voltage in sequence when such potential difference undergoes a progressive change in magnitude.