Patents by Inventor Trevor Robert Elbourne

Trevor Robert Elbourne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6411736
    Abstract: An apparatus is disclosed for decoding a stream of previously encoded coefficients including input means for receiving the stream of encoded coefficients; bit plane level monitoring means connected to the input means and adapted to monitor a current bit plane level from the stream of coefficients; pixel generation means interconnected to the input means and the bit plane level monitoring means and adapted to utilize the current bit plane level for generating output coefficient values each having a predetermined size.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: June 25, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Dominic Yip, Trevor Robert Elbourne
  • Patent number: 6266450
    Abstract: An apparatus for the encoding of a series of wavelet coefficients of a predetermined size into a compact representation of the coefficients. The apparatus comprises a tree builder for constructing a tree form representation of the coefficients with leaf nodes representing coefficient values and internal nodes representing the number of bits needed to encode leaf nodes and child nodes of a current internal node. The tree builder stores the tree form representation in a tree buffer of the apparatus, and the tree buffer stores the tree form representation. A tree coder of the apparatus is interconnected to the tree buffer and adapted to read a current tree form representation and to output the encoding from the tree form representation.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: July 24, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Dominic Yip, Trevor Robert Elbourne, Hiren Patel
  • Patent number: 6195674
    Abstract: An apparatus and a method for performing discrete cosine transformation (DCT) are presented. The apparatus includes an arithmetic circuit interconnected with a transpose memory. The arithmetic circuit includes a combinatorial circuit for calculating a DCT without using an intermediate clocked storage unit. The combinatorial circuit includes a predetermined number of sequentially arranged stages for implementing the DCT. The apparatus may optionally include a controller for controlling operation of the apparatus and a multiplexer for multiplexing data input to the apparatus and data from the transpose memory. An apparatus and a method for performing inverse discrete cosine transformation (IDCT) are also presented.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: February 27, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Trevor Robert Elbourne, Mark Pulver