Abstract: A system and method for checking the test logic contained in a computer memory system during POST such that any errors can be determined and made available to the system software prior to beginning processing operations. Single and double bit errors are induced which the ECC logic must identify and correct. The CPU compares the data that is written to memory with the data that is read back. Thus, since it is known that an error occurred, due to the induced error provided by the present invention, identical data will verify that the ECC correction logic is working properly. More specifically, a multiplexer is provided in the data write path which substitutes a constant set of identical bits for the actual data generated by the CPU. ECC bits are generated based on the actual generated test data, rather than the inserted identical bits. The substituted data bits and generated ECC bits are then stored in memory. An error condition is identified when the data and ECC code is read back from memory.

Abstract: Data bus steering logic routes data between various byte lanes of the system bus. Additionally, control signals are provided which allow the connected device and the steering logic to communicate and respond to requests made by the CPU. The steering logic provides a path between the attached device and the byte lanes of the system bus, to which the device is not directly connected. During load and store operations data is transferred via the steering logic and directly between the device and CPU on to the portion of the system bus that it is directly connected to. The steering logic includes a multiplexer, latch, buffer, driver and the like for each lane of data on the system bus. For example, if the system bus is 64 bits wide and a 32 bit device is connected to one-half of the bus, the steering logic will provide a path from the 32 bit device to the other 32 bits of the system bus not directly connected to the device.