Abstract: A talking watch device for helping a user learn time comprising a base having a clock face; a quartz oscillator assembly; a digital counter operatively connected to the quartz oscillator assembly and to a microprocessor, the digital counter keeps track of a time, day, month, and year component; a memory medium for storing a plurality of audio messages; a speaker component operatively connected to a digital to analog converter; and a dial operatively connected to the microprocessor, the dial can move between a first position, a second position, a third position, and a fourth position, wherein the microprocessor is configured to receive input signals from the dial whereupon the microprocessor generates output commands to the speaker to play a time component message and/or a day component message and/or a month component message and/or a year component message.

Abstract: According to one embodiment, a debugging tool includes a processor and logic, that when executed by the processor, causes the processor to: receive a Volume Table of Contents (VTOC)/INDEX data set for a first VTOC/INDEX data of a remote system, create second VTOC/INDEX data (which is a replicated version of the first VTOC/INDEX data of the remote system) from the VTOC/INDEX data set, execute a second scenario (which is a replicated version of a first scenario that was executed on the remote system using the first VTOC/INDEX data that caused the error) using the second VTOC/INDEX data to reproduce an error, and set up trace points in the second VTOC/INDEX data to start a debugging session while executing the second scenario using the second VTOC/INDEX data. Other systems, methods, and computer program products are also described according to various other embodiments.

Abstract: A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.

Abstract: According to one embodiment, a debugging tool includes a processor and logic, that when executed by the processor, causes the processor to: receive a Volume Table of Contents (VTOC)/INDEX data set for a first VTOC/INDEX data of a remote system, create second VTOC/INDEX data (which is a replicated version of the first VTOC/INDEX data of the remote system) from the VTOC/INDEX data set, execute a second scenario (which is a replicated version of a first scenario that was executed on the remote system using the first VTOC/INDEX data that caused the error) using the second VTOC/INDEX data to reproduce an error, and set up trace points in the second VTOC/INDEX data to start a debugging session while executing the second scenario using the second VTOC/INDEX data. Other systems, methods, and computer program products are also described according to various other embodiments.

Abstract: A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.

Abstract: A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is partitioned into a plurality of regions, each of the plurality of regions comprises more than one bit of the first plurality of bits. A leading zero anticipator or other type of leading bit indication circuit is coupled to each region and determines a position of a leading bit of the first plurality of bits. A normalizer is coupled to receive a region of the plurality of regions that contains the leading bit, the normalizer may normalize or denormalize the region to produce a normalized or denormalized floating point number.

Abstract: A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.

Abstract: A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.

Abstract: A method of automatically invoking a recoverable and fault tolerant implementation of the complemented/recomplemented (C/R) error correction method without the assistance of a service processor when an excessive error is detected in main storage (MS) by ECC logic circuits. An excessive error is not correctable by the ECC. These novel changes to the C/R method increase its effectiveness and protect the C/R hardware against random failure. Further, if an excessive error is corrected in a page in MS, an excessive error reporting process is provided for controlling the reporting using a storage map to determine if a previous correction in that page has been reported. If it has been reported, then no further reporting of soft excessive errors is made for that page. A service processor is signaled in parallel to update its persistent copy of the storage map so that on a next initializations of MS the memory map can be restored in the memory.