Patents by Inventor Tristan TRONIC

Tristan TRONIC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS OF FORMING THIN FILM RESISTOR STRUCTURES UTILIZING INTERCONNECT LINER MATERIALS
    Publication number: 20190326214
    Abstract: Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.
    Type: Application
    Filed: December 29, 2016
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Kevin Lin, Christopher J. Jezewski, Richard F. Vreeland, Tristan A. Tronic
  • MASKLESS AIR GAP TO PREVENT VIA PUNCH THROUGH
    Publication number: 20190189500
    Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
    Type: Application
    Filed: February 25, 2019
    Publication date: June 20, 2019
    Inventors: Manish CHANDHOK, Todd R. YOUNKIN, Eungnak HAN, Jasmeet S. CHAWLA, Marie KRYSAK, Hui Jae YOO, Tristan A. TRONIC
  • Maskless air gap to prevent via punch through
    Patent number: 10256141
    Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Todd R. Younkin, Eungnak Han, Jasmeet S. Chawla, Marie Krysak, Hui Jae Yoo, Tristan A. Tronic
  • MASKLESS AIR GAP TO PREVENT VIA PUNCH THROUGH
    Publication number: 20180204760
    Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
    Type: Application
    Filed: September 23, 2015
    Publication date: July 19, 2018
    Inventors: Manish CHANDHOK, Todd R. YOUNKIN, Eungnak HAN, Jasmeet S. (JZ) CHAWLA, Marie KRYSAK, Hui Jae YOO, Tristan A. TRONIC