Abstract: The invention provides a method for automatically analyzing and filtering redundant alarms in radio transceiver systems consisting of the following steps: step 1: the operator shall define the relationship between the alarms, defining rules to filter redundant alarms at the FRDU block; step 2: the FSU block will detect the alarm and send it to the FAFU block; step 3: FAFU block will receive alarms from FSU, based on the rules defined in FRDU block will analyze and filter out redundant alarms; Step 4: The FSMU block will receive the alarms after being filtered, stored in the database and also send these alarms to the EMS system.

Abstract: The invention provides a method for automatically analyzing and filtering redundant alarms in radio transceiver systems consisting of the following steps: step 1: the operator shall define the relationship between the alarms, defining rules to filter redundant alarms at the FRDU block; step 2: the FSU block will detect the alarm and send it to the FAFU block; step 3: FAFU block will receive alarms from FSU, based on the rules defined in FRDU block will analyze and filter out redundant alarms; Step 4: The FSMU block will receive the alarms after being filtered, stored in the database and also send these alarms to the EMS system.

Abstract: A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

Abstract: During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.

Abstract: A signal delay device is provided which enhances noise immunity by using a differential circuit, but also maintains the phase of the input clock signals. This device will also correct the phase of clock signals which are input to the delay device in an out of phase condition. The present invention is a delay circuit that includes functionally connecting each of the output signals with each of the input signals. Thus, the output signals are dependent on the same input and the steady state condition is the point where the leading edge of a first output signal intersects the trailing edge of a second output signal at the point which corresponds to one half of the pulse height of both signals. Since the signals are complements of one another, they will cross at 50% of their pulse height when they are "in phase". Thus, the present invention will maintain "in phase" input signals and seek an "in phase" condition for signals that are input to the delay circuit which are "out of phase".