Abstract: A current-mode direct conversion RF receiver is presented. In one set of embodiments the RF receiver comprises a simple transconductor input stage to create a current-mode modulated signal from a voltage-mode modulated signal. A downconversion mixer may be coupled to the transconductor input stage via a low impedance current cascode stage, and may operate to create a set of current-mode quadrature baseband signals from the current-mode modulated signal. The downconversion mixer may be implemented with a transistor-switching network, which may be driven by a phase locked loop (PLL) with quadrature outputs. The set of current-mode quadrature baseband signals may be converted back to the voltage domain by a transimpedance filter, which may perform channel selection for the receiver. The transimpedance filter may additionally include a low frequency zero to remove DC offsets.

Abstract: A radio transmitter system designed using an FSK modulator with IQ up-mixers and sinewave coded digital-to-analog converters (DACs). The radio transmitter system may include a frequency shift keying (FSK) coding logic circuit coupled to the inputs of an IQ modulation and image reject up-mixer through a respective DAC and a respective low pass filter (LPF) for each the I and the Q channels. The FSK modulation scheme may employ sine and cosine signals for the I and Q channels, respectively, where the sine and cosine waves are directly coded into the DACs. The coded levels required by the DACs may be generated using current sources and may be Gray-coded. The output of the IQ modulation and image reject up-mixer may be connected to a power amplifier, which may be used to transmit the modulated RF signal via a loop antenna.

Abstract: The present invention discloses a low voltage rail-to-rail CMOS input stage. The input stage includes a differential pail of P-channel metal oxide semiconductor field effect (PMOS) transistors, which produces differential output current signal. The input stage further includes a pair of N-channel depletion-mode metal oxide semiconductor field effect (NMOS) transistors, coupled to the bulk terminals of the differential pair of PMOS transistors, for receiving an input signal. The depletion-mode NMOS transistors further act as source follower devices to drive the bulk terminals of the differential pair of PMOS transistors.

Abstract: A temperature to digital converter device is implemented by integrating a temperature sensor circuit into an analog-to-digital converter (ADC). Temperature-to-digital conversion is accomplished by first measuring a change in voltage (?VBE) across the junction of a diode when different current densities are forced through the junction. The thus obtained ?VBE is proportional to temperature. As part of the conversion processing, ?VBE is multiplied by a fixed gain, and an offset voltage value is subtracted from ?VBE. The multiplication and subtraction functions are performed by a switched-capacitor integrator in a delta-sigma ADC and the ADC itself operates as the temperature-to-digital converter device, eliminating the extra amplifier and/or capacitors required when the multiplication and/or subtraction function are performed outside the ADC. Alternately, other ADC topologies that include an integrator or gain amplifier, such as pipeline ADCs and cyclic ADCs may be used in place of the delta-sigma ADC.

Abstract: An integrated circuit includes circuit nodes (111 and 131), a resistor (210) coupling together the nodes, a comparator (230) having two inputs and an output where a first one of the two inputs is coupled to the resistor and a first one of the nodes, and a three-terminal device (220) having a first terminal coupled to a second one of the nodes and the resistor and also having a second terminal coupled to the output of the comparator.

Abstract: A filter circuit. In one embodiment, the filter circuit includes a continuous time (CT) filter, a switched capacitor (SWC) filter, and an SWC integrator. The CT filter is coupled to receive an input signal from an external source. The CT filter may be a low-pass filter. The SWC filter is coupled to receive an output signal from the CT filter, and provide an output information signal. The SWC filter may also be a low pass filter. A feedback loop may be present between the output of the SWC filter and the input of the CT filter. The SWC integrator samples the output signal from the SWC filter and provides an output signal to the CT filter. The output signal is combined with the input signal to the CT filter. A D.C. offset may be substantially removed from the information signal provided by the output of the SWC filter.

Abstract: An output stage suitable for low voltage operation and capable of providing an essentially symmetrical rail-to-rail output voltage including a first field effect device having a first drain, a first gate, and a first source coupled to a power supply VCC. The output stage further includes a second field effect device complimentary to the first field effect device, having a second drain, a second gate, and a second source coupled to a power supply having a nominal voltage of VEE. Further, the second drain is coupled to the first drain. Further, the output stage is an output sink network coupled to the second field effect device. The output sink network drives the second field effect device such that a current is produced in the first field effect device and a current in the second field effect device is essentially equal to a predetermined constant during operation of the output stage.

Abstract: An integrated circuit (100, 200, 300) includes a voltage-mode driver circuit having an analog on-chip termination and also having a substantially constant output impedance across an operating range of an output voltage of the voltage-mode driver circuit. The voltage-mode driver circuit also has slew rate control of the output voltage.

Abstract: The present invention discloses a low voltage rail-to-rail CMOS input stage. The input stage includes a differential pail of P-channel metal oxide semiconductor field effect (PMOS) transistors, which produces differential output current signal. The input stage further includes a pair of N-channel depletion-mode metal oxide semiconductor field effect (NMOS) transistors, coupled to the bulk terminals of the differential pair of PMOS transistors, for receiving an input signal. The depletion-mode NMOS transistors further act as source follower devices to drive the bulk terminals of the differential pair of PMOS transistors.

Abstract: The present invention discloses a low voltage rail-to-rail CMOS input stage. The input stage includes a differential pail of P-channel metal oxide semiconductor field effect (PMOS) transistors, which produces differential output current signal. The input stage further includes a pair of N-channel depletion-mode metal oxide semiconductor field effect (NMOS) transistors, coupled to the bulk terminals of the differential pair of PMOS transistors, for receiving an input signal. The depletion-mode NMOS transistors further act as source follower devices to drive the bulk terminals of the differential pair of PMOS transistors.

Abstract: An output stage suitable for low voltage operation and capable of providing an essentially symmetrical rail-to-rail output voltage is disclosed. The output stage includes a first field effect device having a first drain, a first gate, and a first source coupled to a power supply VCC. The output stage further includes a second field effect device complimentary to the first field effect device, having a second drain, a second gate, and a second source coupled to a power supply having a nominal voltage of VEE. Further, the second drain is coupled to the first drain. Also included in the output stage is an output sink network coupled to the second field effect device. The output sink network drives the second field effect device such that a product of a current in the first field effect device and a current in the second field effect device is essentially equal to a predetermined constant during operation of the output stage.

Abstract: A battery protection system (20) controls a process for charging a battery pack (15). A hysteresis comparator (54) senses a charging current flowing through the battery pack (15) and switches off a charging switch (31) to interrupt the charging current when the charging current reaches an upper limit. A transient current is then generated by an inductor (34). The hysteresis comparator (54) senses the transient current flowing through the battery pack (15) and switches on the charging switch (31) to regenerate the charging current when the transient current decreases substantially to zero. Periodically, a battery monitoring circuit (40) switches off the charging switch (31) and measures an open circuit voltage across each battery cell in the battery pack (15). In response to the open circuit voltage of a battery cell reaching a fully charged voltage, the battery monitoring circuit (40) switches off the charging switch (31) to terminate the charging process.

Abstract: A battery protection system (20) controls a process for charging a battery pack (15). A hysteresis comparator (54) senses a charging current flowing through the battery pack (15) and switches off a charging switch (31) to interrupt the charging current when the charging current reaches an upper limit. A transient current is then generated by an inductor (34). The hysteresis comparator (54) senses the transient current flowing through the battery pack (15) and switches on the charging switch (31) to regenerate the charging current when the transient current decreases substantially to zero. Periodically, a battery monitoring circuit (40) switches off the charging switch (31) and measures an open circuit voltage across each battery cell in the battery pack (15). In response to the open circuit voltage of a battery cell reaching a fully charged voltage, the battery monitoring circuit (40) switches off the charging switch (31) to terminate the charging process.

Abstract: An overcurrent detector circuit (21) for a power MOSFET (22) is described. The overcurrent detector circuit (21) generates a bias voltage corresponding to the drain to source voltage of the power MOSFET (22). The drain to source voltage correlates directly to the current being conducted by the power MOSFET (22). An overcurrent condition occurs when the power MOSFET (22) exceeds a predetermined current. The bias voltage is applied to a transistor (24) for generating a current. A current source (29) couples to the transistor (24). The current provided by the transistor equals the reference current of the current source (29) when the power MOSFET conducts the predetermined current. The overcurrent detector circuit (21) generates a signal indicating a overcurrent condition does not exist when the reference current is greater the current provided by the transistor.

Abstract: A protocol between a microprocessor (21) and an interface circuit (11). The interface circuit (11) transmits an enable signal (124) to the microprocessor (21). Upon receiving the enable signal (124), the microprocessor (21) transmits a set of pulses of a window signal (125) to the interface circuit (11), which in turn provides the microprocessor (21) with information concerning a circuit element (36) through a data signal (127). The microprocessor (21) initiates a command by transmitting a pulse of a command signal (126) to the interface circuit (11). The interface circuit (11) accepts and executes the command only if a predetermined chronological condition between the pulse of the command signal (126) and a corresponding pulse of the window signal (125) is satisfied. The microprocessor (21) identifies a malfunctioning interface circuit (11) by timing the enable signal (124) received from the interface circuit (11).

Abstract: A power source balancing circuit (10) balances two power sources such as two battery cells (12 and 42). When the power source balancing circuit (10) is enabled, it compares a current flowing through the first battery cell (12) and a first resistor (22) with a current flowing through the second battery cell (42) and a second resistor (52). Because the resistance of the first resistor (22) is equal to that of the second resistor (52), a difference between the two currents indicates a difference between the voltages of the two battery cells (12 and 42). If a current difference larger than a predetermined limit is detected, the battery cell (12 or 42) with a higher voltage is discharged through a corresponding discharge resistor (14 or 44) by switching on a corresponding switch (16 or 46). The corresponding switch (16 or 46) is controlled by a corresponding flip-flop (32 or 62).

Abstract: A battery monitoring circuit (10) sequentially samples individual voltages across a string of serially coupled battery cells (12-18). A control circuit (32) controls first and second multiplexers (34,42) to sample each battery voltage for an over-voltage condition. A comparator (52) detects an over-voltage condition by comparing a divided down battery voltage against a reference. The conduction path through the battery cells is disabled upon detecting a fault condition by a transistor (26) in the battery cell conduction path. The battery cells are further sequentially sampled for an under-voltage fault. The comparator detects an under-voltage condition by comparing a second divided down battery voltage against the reference. The conduction path through the battery cells is disabled upon detecting a fault condition by a transistor (24) in the battery cell conduction path.

Abstract: A voltage regulator (11) having an input (12) for receiving an input current and an output (13) for providing a regulated voltage. The voltage regulator (11) comprising a diode (14), a capacitor (16), a first comparator (17), a second comparator (18), a logic circuit (19), and a switch circuit (21). The capacitor (16) is charged by the input current coupled through the diode (14). The first comparator (17) senses when the voltage on the capacitor (16) exceeds a first reference voltage and provides a signal to the logic circuit (19). The logic circuit (19) enables the switch circuit (21) for shunting the input current from charging the capacitor (19). The second comparator (18) senses when the voltage on the capacitor (16) falls below a second reference voltage and provides a signal to the logic circuit (19). The logic circuit (19) disables the switch circuit (21) from shunting the input current thereby charging the capacitor (19).

Abstract: An amplifier circuit (10) receives a differential input signal and provides an amplified differential signal. A converter circuit (14) is responsive to the amplified differential signal and provides a single-ended signal. An output stage (16) is responsive to the single-ended signal for providing an output signal of the amplifier circuit. The output stage provides bias cancellation for the single-ended signal by injecting a current equal to the bias requirement of the input transistors (20, 38). The bias cancellation maintains a high input impedance and high gain and output drive for the output stage.

Abstract: A TC controlled RF signal detecting circuitry (211) used in the output power control circuit of a TDMA RF signal power amplifier includes positive coefficient current source (303) producing current I+ having a positive TC, negative coefficient current source (305) producing current I- having a negative TC, and current mirror (301) for summing currents I+ and I- to produce substantially identical compensated mirror currents Im1 and Im2. Anti-clamping current mirror (309) mirrors current Im2 to produce compensated currents Ia1 and Ia2, which are applied to and bias a Schottky diode coupled in series to a resistor network in each leg of diode detector (311). Each leg of diode detector (311) has a positive TC, which is substantially offset by the negative TC of compensated currents Ia1 and Ia2.