Patents by Inventor Troy N. Gilliland
Troy N. Gilliland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9767861Abstract: A circuit provides a regulated voltage supply for other circuits. The circuit includes a bias current source and a reference voltage source. The circuit includes a pass transistor and a feedback transistor. The pass transistor receives input from the feedback transistor that generates a regulated voltage at a terminal of the pass transistor. The feedback transistor receives inputs from the regulated voltage of the pass transistor and the reference voltage source. The feedback transistor provides voltage for the input of the pass transistor, thereby controlling the regulated voltage generated by the pass transistor. The regulated voltage generated by the pass transistor is provided as a regulated voltage supply to other circuits.Type: GrantFiled: July 28, 2015Date of Patent: September 19, 2017Assignee: Synopsys, Inc.Inventors: Troy N. Gilliland, Yanyi Liu Wong
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Publication number: 20170033687Abstract: A circuit provides a regulated voltage supply for other circuits. The circuit includes a bias current source and a reference voltage source. The circuit includes a pass transistor and a feedback transistor. The pass transistor receives input from the feedback transistor that generates a regulated voltage at a terminal of the pass transistor. The feedback transistor receives inputs from the regulated voltage of the pass transistor and the reference voltage source. The feedback transistor provides voltage for the input of the pass transistor, thereby controlling the regulated voltage generated by the pass transistor. The regulated voltage generated by the pass transistor is provided as a regulated voltage supply to other circuits.Type: ApplicationFiled: July 28, 2015Publication date: February 2, 2017Inventors: Troy N. Gilliland, Yanyi Liu Wong
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Patent number: 9553207Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.Type: GrantFiled: September 25, 2013Date of Patent: January 24, 2017Assignee: Synopsys, Inc.Inventors: Andrew E. Horch, Troy N. Gilliland
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Publication number: 20150085585Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.Type: ApplicationFiled: September 25, 2013Publication date: March 26, 2015Applicant: Synopsys, Inc.Inventors: Andrew E. Horch, Troy N. Gilliland
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Patent number: 8743626Abstract: Controlling a non-volatile memory. The non-volatile memory includes a plurality of memory cells in an integrated circuit substrate. The non-volatile memory also includes a high-voltage node in power-transmissive communication with the plurality of memory cells. Further, the non-volatile memory includes an intermediate-voltage node in power-transmissive communication with the plurality of memory cells. Moreover, the non-volatile memory includes a counter-doped-gate device, coupled within the integrated circuit substrate, in power-transmissive communication between the high-voltage node and the intermediate-voltage node.Type: GrantFiled: February 18, 2011Date of Patent: June 3, 2014Assignee: Synopsys, Inc.Inventors: Yanyi L. Wong, Troy N. Gilliland
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Publication number: 20130002343Abstract: High voltage regulation in charge pumps. A circuit includes a voltage regulator with a first input in communication with a reference voltage. The circuit also includes a data latch having a signal input coupled to receive an output of the voltage regulator and coupled to receive a clock input from a clock source. The circuit further includes a delay circuit having an input coupled to receive the clock input from the clock source. Further, the circuit includes a logic gate having a first input coupled with an output of the data latch and a second input coupled with an output of the delay circuit. Moreover, the circuit includes a charge pump having an input coupled with an output of the logic gate and an output coupled with a second input of the voltage regulator. The output of the charge pump provides an output voltage.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: SYNOPSYS INC.Inventors: Yanyi L. WONG, Troy N. Gilliland
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Publication number: 20120213007Abstract: Controlling a non-volatile memory. The non-volatile memory includes a plurality of memory cells in an integrated circuit substrate. The non-volatile memory also includes a high-voltage node in power-transmissive communication with the plurality of memory cells. Further, the non-volatile memory includes an intermediate-voltage node in power-transmissive communication with the plurality of memory cells. Moreover, the non-volatile memory includes a counter-doped-gate device, coupled within the integrated circuit substrate, in power-transmissive communication between the high-voltage node and the intermediate-voltage node.Type: ApplicationFiled: February 18, 2011Publication date: August 23, 2012Applicant: SYNOPSYS INC.Inventors: Yanyi L. WONG, Troy N. Gilliland
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Patent number: 7573749Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.Type: GrantFiled: March 29, 2007Date of Patent: August 11, 2009Assignee: Virage Logic CorporationInventors: Christopher J. Diorio, Chad A. Lindhorst, Shailendra Srinivas, Alberto Pesavento, Troy N. Gilliland
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Patent number: 7289358Abstract: Non-Volatile Memory (NVM) cells include a selection circuit for providing an output based on selecting between an input data signal and an output of a Multiple Time Programmable (MTP) NVM element. The input data signal may be latched by a latch circuit such as a flip-flop first. The selector circuit's output is used to confirm the programming values for the MTP NVM element such that the element can be programmed correctly without losing time by reading the programmed MTP NVM element or reprogramming a misprogrammed element.Type: GrantFiled: January 18, 2006Date of Patent: October 30, 2007Assignee: Impinj, Inc.Inventors: Alberto Pesavento, Troy N. Gilliland, Frederic J. Bernard
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Patent number: 7212446Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.Type: GrantFiled: April 21, 2004Date of Patent: May 1, 2007Assignee: Impinj, Inc.Inventors: Christopher J. Diorio, Chad A. Lindhorst, Shailendra Srinivas, Alberto Pesavento, Troy N. Gilliland
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Patent number: 7145370Abstract: Circuits are provided for high-voltage switching in single-well CMOS processes.Type: GrantFiled: March 30, 2004Date of Patent: December 5, 2006Assignee: Impinj, Inc.Inventors: Frédéric J. Bernard, Christopher J. Diorio, Troy N. Gilliland, Alberto Pesavento, Kaila G Raby, Terry D. Hass, John D. Hyde
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Patent number: 6950342Abstract: A number of designs for differential floating gate nonvolatile memories and memory arrays utilize differential pFET floating gate transistors to store information. Methods of implementing such memories and memory arrays together with methods of operation and test associated with such memories and memory arrays are presented.Type: GrantFiled: May 12, 2003Date of Patent: September 27, 2005Assignee: Impinj, Inc.Inventors: Chad A. Lindhorst, Christopher J. Diorio, Troy N. Gilliland, Alberto Pesavento, Shail Srinivas, Yanjun Ma, Terry Hass, Kambiz Rahimi
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Publication number: 20040195593Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.Type: ApplicationFiled: April 21, 2004Publication date: October 7, 2004Applicant: Impinj, Inc., a Delaware CorporationInventors: Christopher J. Diorio, Chad A. Lindhorst, Shailendra Srinivas, Alberto Pesavento, Troy N. Gilliland
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Publication number: 20040037127Abstract: A number of designs for differential floating gate nonvolatile memories and memory arrays utilize differential pFET floating gate transistors to store information. Methods of implementing such memories and memory arrays together with methods of operation and test associated with such memories and memory arrays are presented.Type: ApplicationFiled: May 12, 2003Publication date: February 26, 2004Applicant: Impinj, Inc., A Delaware CorporationInventors: Chad A. Lindhorst, Christopher J. Diorio, Troy N. Gilliland, Alberto Pesavento, Shail Srinivas, Yanjun Ma, Terry Hass, Kambiz Rahimi
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Patent number: 6255902Abstract: An amplifier circuit with small die size and low power consumption is described. The design allows a number of switch amplifier circuits to be placed on a single chip. Each of the amplifiers contains a comparator for greater amplification, with a designed-in offset, a small pull-down current, and a diode. The comparators are biased with low current values and the need for large resistors is eliminated. Several such devices can be placed on a chip along with an edge triggered shift register to store the logic levels generated from the switch inputs. The offset, either built-in or externally supplied, sets one comparator input to an offset voltage. The switch is connected to the other input, with the diode and pull-down in parallel between this input and ground or other reference level: When the switch is open, the pull-down takes the input to ground; when the switch is closed, the diode voltage drop holds the input to a voltage above the offset.Type: GrantFiled: February 23, 2000Date of Patent: July 3, 2001Assignee: Zilog, Inc.Inventors: Troy N. Gilliland, Steven L. Holmes