Abstract: For use in a processor having separate instruction and data buses, separate instruction and data memories and separate instruction and data units, a mechanism for, and method of, supporting self-modifying code and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a crosstie bus coupling the instruction bus and the data unit and (2) a request arbiter, coupled between the instruction and data units, that arbitrates requests therefrom for access to the instruction memory.

Abstract: A system that allows the continuous accessing of data on a floating point processor unit (FPU), by providing two data ports and corresponding buses between the data cache and the FPU. Further, synchronization between the fixed point unit (FXU), which provides the addresses, and the FPU is provided so that data can be loaded in the event of a data cache miss. This synchronization allows data to be transferred from the DCU to the FPU independent of an error condition (cache miss) on one of the buses. If a cache miss occurs that affects a first one of the buses, then the instruction corresponding to this data is held. Subsequent floating point data is received by the FPU on the second bus not subject to the miss. Synchronization signals include, load ready (LD1.sub.-- RDY) indicating to the FPU that data is on the bus and ready to be moved to the FPU and load not ready (LD1.sub.

Abstract: A data processing system is provided that includes a plurality of execution units each including independent circuits for storing and executing instructions. A circuit is also included for providing instructions from a sequence of instructions to the execution units where each instruction is provided to only one of the execution units. The system includes a circuit for detecting when an instruction in a first execution unit must complete execution prior to execution of an instruction in a second execution unit to produce correct results. A circuit is further included, responsive to the circuit for detecting, for delaying executing the instruction in the second execution unit until the instruction in the first execution unit has completed execution.

Abstract: A data processing system having an instruction execution circuit that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.