Abstract: This invention relates to a novel optoelectronic chip with one or more optoelectronic devices, such as photodiodes, fabricated on a front side of a semiconductor wafer and contacts on a backside of the semiconductor wafer. The backside contacts can be contact bumps, which allow the optoelectronic chip to achieve the benefits of flip chip packaging without flipping the optoelectronic chip upside down with respect to a chip carrier. In an optical communication system, a photodiode chip can be backside bumped to a chip carrier or an electronic chip, allowing front side illumination of the photodiode chip. Front side illumination offers many benefits, including improved fiber alignment, reduced manufacturing time, and overall cost reduction.

Abstract: This invention relates to a novel optoelectronic chip with one or more optoelectronic devices, such as photodiodes, fabricated on a front side of a semiconductor wafer and contacts on a backside of the semiconductor wafer. The backside contacts can be contact bumps, which allow the optoelectronic chip to achieve the benefits of flip chip packaging without flipping the optoelectronic chip upside down with respect to a chip carrier. In an optical communication system, a photodiode chip can be backside bumped to a chip carrier or an electronic chip, allowing front side illumination of the photodiode chip. Front side illumination offers many benefits, including improved fiber alignment, reduced manufacturing time, and overall cost reduction.

Abstract: This invention relates to a novel optoelectronic chip with one or more optoelectronic devices, such as photodiodes, fabricated on a front side of a semiconductor wafer and contacts on a backside of the semiconductor wafer. The backside contacts can be contact bumps, which allow the optoelectronic chip to achieve the benefits of flip chip packaging without flipping the optoelectronic chip upside down with respect to a chip carrier. In an optical communication system, a photodiode chip can be backside bumped to a chip carrier or an electronic chip, allowing front side illumination of the photodiode chip. Front side illumination offers many benefits, including improved fiber alignment, reduced manufacturing time, and overall cost reduction.

Abstract: A detector with a transistor sensitive to electromagnetic energy. In accordance with the present teachings, the transistor is biased such that the output thereof is responsive to the electromagnetic energy. The inventive imager includes an array of the novel detectors. Each of the detectors being an n-channel metal-oxide semiconductor transistor with a floating body. The transistors are biased for selective activation and sequential readout. The transistor outputs are read by a differential current sense amplifier. A color filter is disclosed to provide a color sense capability. As an alternative, a grating is provided for this purpose. The present invention allows a very dense imager to be built on using conventional silicon on sapphire or silicon on insulator complementary metal-oxide semiconductor processes. The use of standard CMOS processes allows for low manufacturing costs.

Abstract: A method that uses effective widths of NMOS and PMOS devices in a digital circuit and their intrinsic junction and subthreshold leakage currents to produce a specification for IDDQ, the range of IDDQ, and the delta of IDDQ between pre- and post-overvoltage stress tests to screen out defective integrated circuits having excessive extrinsic current leakage. The present invention provides for a computer-implemented method that generates an indication of whether IDDQ values associated with integrated circuits that have been tested are within the IDDQ specification or not. This processing eliminates the need for time-intensive and costly burn-in testing on the integrated circuits.

Abstract: A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both a fabrication and structural complexity favorably comparable to conventional CMOS devices which are not radiation-hard. A method for fabricating the device is disclosed.

Abstract: The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions.

Abstract: The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions.

Abstract: A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions.