Patents by Inventor Tsai-Hao Hung
Tsai-Hao Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11963368Abstract: A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.Type: GrantFiled: May 25, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Chieh Mo, Shih-Chi Kuo, Tsai-Hao Hung
-
Patent number: 11955501Abstract: The present disclosure describes a method for the formation of mirror micro-structures on radiation-sensing regions of image sensor devices. The method includes forming an opening within a front side surface of a substrate; forming a conformal implant layer on bottom and sidewall surfaces of the opening; growing a first epitaxial layer on the bottom and the sidewall surfaces of the opening; depositing a second epitaxial layer on the first epitaxial layer to fill the opening, where the second epitaxial layer forms a radiation-sensing region. The method further includes depositing a stack on exposed surfaces of the second epitaxial layer, where the stack includes alternating pairs of a high-refractive index material layer and a low-refractive index material layer.Type: GrantFiled: June 6, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Yu Liao, Tsai-Hao Hung, Ying-Hsun Chen
-
Publication number: 20240087945Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Tsai-Hao HUNG, Ping-Cheng KO, Tzu-Yang LIN, Fang-Yu LIU, Cheng-Han WU
-
Patent number: 11923396Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.Type: GrantFiled: April 18, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Wei Hsu, Tsai-Hao Hung, Chung-Yu Lin, Ying-Hsun Chen
-
Publication number: 20240063251Abstract: A semiconductor device includes a substrate, a first multilayer capacitor, and a second multilayer capacitor. The first multilayer capacitor includes a first plurality of conductive layers. The semiconductor device further includes a first set of contacts including a first contact electrically connected to a first conductive layer, and a second contact electrically connected to a second conductive layer, wherein the first contact is spaced from the second contact by a first distance. The second multilayer capacitor includes a second plurality of conductive layers. The semiconductor device further includes a second set of contacts including a third contact electrically connected to a third conductive layer, and a fourth contact electrically connected to a fourth conductive layer, wherein the third contact is spaced from the fourth contact by a second distance, and the second distance is different from the first distance.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Inventors: Tao-Cheng LIU, Shih-Chi KUO, Tsai-Hao HUNG, Tsung-Hsien LEE
-
Patent number: 11854860Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.Type: GrantFiled: November 15, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsai-Hao Hung, Ping-Cheng Ko, Tzu-Yang Lin, Fang-Yu Liu, Cheng-Han Wu
-
Publication number: 20230411463Abstract: Integrated semiconductor devices and method of making the integrated semiconductor are disclosed. The integrated semiconductor device may include a first transistor comprising a first gate and at least one first active region, a second transistor comprising a second gate and at least one second active region, wherein the second transistor is spaced a first distance from the first transistor, a dielectric sidewall spacer formed on a gate sidewall of the first transistor and a gate sidewall of the second transistor, a first dielectric layer formed over the first transistor and the second transistor, wherein a thickness of the first dielectric layer is greater than half the first distance, and a patterned metal layer formed on the first dielectric layer and partially covering the second gate.Type: ApplicationFiled: August 1, 2023Publication date: December 21, 2023Inventors: Chien-Hung LIN, Tsai-Hao HUNG
-
Publication number: 20230396189Abstract: A micromechanical arm array is provided. The micromechanical arm array comprises: a plurality of micromechanical arms spaced from each other in a first horizontal direction and extending in a second horizontal direction, wherein each micromechanical arm comprises a protrusion at a top of each micromechanical arm and protruding upwardly in a vertical direction; a plurality of protection films, each protection film encapsulating one of the plurality of micromechanical arms; and a metal connection structure extending in the first horizontal direction. The metal connection structure comprises: a plurality of joint portions, each joint portion corresponding to and surrounding the protrusion of one of the plurality of micromechanical arms; and a plurality of connection portions extending in the first horizontal direction and connecting two neighboring joint portions.Type: ApplicationFiled: August 3, 2023Publication date: December 7, 2023Inventors: Shih-Yu Liao, Tsai-Hao Hung
-
Publication number: 20230375416Abstract: The structure of a micro-electro-mechanical system (MEMS) thermal sensor and a method of fabricating the MEMS thermal sensor are disclosed. A method of fabricating a MEMS thermal sensor includes forming first and second sensing electrodes with first and second electrode fingers, respectively, on a substrate and forming a patterned layer with a rectangular cross-section between a pair of the first electrode fingers. The first and second electrode fingers are formed in an interdigitated configuration and suspended above the substrate. The method further includes modifying the patterned layer to have a curved cross-section between the pair of the first electrode fingers, forming a curved sensing element on the modified patterned layer to couple to the pair of the first electrodes, and removing the modified patterned layer.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Tsai-Hao HUNG, Shih-Chi KUO
-
Patent number: 11810945Abstract: A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.Type: GrantFiled: December 9, 2020Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao-Cheng Liu, Shih-Chi Kuo, Tsai-Hao Hung, Tsung-Hsien Lee
-
Patent number: 11796396Abstract: The structure of a micro-electro-mechanical system (MEMS) thermal sensor and a method of fabricating the MEMS thermal sensor are disclosed. A method of fabricating a MEMS thermal sensor includes forming first and second sensing electrodes with first and second electrode fingers, respectively, on a substrate and forming a patterned layer with a rectangular cross-section between a pair of the first electrode fingers. The first and second electrode fingers are formed in an interdigitated configuration and suspended above the substrate. The method further includes modifying the patterned layer to have a curved cross-section between the pair of the first electrode fingers, forming a curved sensing element on the modified patterned layer to couple to the pair of the first electrodes, and removing the modified patterned layer.Type: GrantFiled: March 29, 2021Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsai-Hao Hung, Shih-Chi Kuo
-
Patent number: 11757378Abstract: A micromechanical arm array is provided. The micromechanical arm array comprises: a plurality of micromechanical arms spaced from each other in a first horizontal direction and extending in a second horizontal direction, wherein each micromechanical arm comprises a protrusion at a top of each micromechanical arm and protruding upwardly in a vertical direction; a plurality of protection films, each protection film encapsulating one of the plurality of micromechanical arms; and a metal connection structure extending in the first horizontal direction. The metal connection structure comprises: a plurality of joint portions, each joint portion corresponding to and surrounding the protrusion of one of the plurality of micromechanical arms; and a plurality of connection portions extending in the first horizontal direction and connecting two neighboring joint portions.Type: GrantFiled: June 6, 2022Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yu Liao, Tsai-Hao Hung
-
Patent number: 11688754Abstract: Photonic devices and methods having an increased quantum effect length are provided. In some embodiments, a photonic device includes a substrate having a first surface. A cavity extends into the substrate from the first surface to a second surface. A semiconductor layer is disposed on the second surface in the cavity of the substrate, and a cover layer is disposed on the semiconductor layer. The semiconductor layer is configured to receive incident radiation through the substrate and to totally internally reflect the radiation at an interface between the semiconductor layer and the cover layer.Type: GrantFiled: May 6, 2020Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsai-Hao Hung, Tao-Cheng Liu, Ying-Hsun Chen
-
Publication number: 20230152521Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.Type: ApplicationFiled: January 9, 2023Publication date: May 18, 2023Inventors: Tao-Cheng LIU, Tsai-Hao HUNG, Shih-Chi KUO
-
Patent number: 11611039Abstract: A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.Type: GrantFiled: August 18, 2021Date of Patent: March 21, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsai-Hao Hung, Shih-Chi Kuo
-
Publication number: 20230077331Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.Type: ApplicationFiled: November 15, 2022Publication date: March 16, 2023Inventors: Tsai-Hao HUNG, Ping-Cheng KO, Tzu-Yang LIN, Fang-Yu LIU, Cheng-Han WU
-
Patent number: 11585982Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.Type: GrantFiled: February 22, 2021Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Shih-Chi Kuo
-
Publication number: 20230045468Abstract: Integrated semiconductor devices and method of making the integrated semiconductor are disclosed. The integrated semiconductor device may include a first transistor comprising a first gate and at least one first active region, a second transistor comprising a second gate and at least one second active region, wherein the second transistor is spaced a first distance from the first transistor, a dielectric sidewall spacer formed on a gate sidewall of the first transistor and a gate sidewall of the second transistor, a first dielectric layer formed over the first transistor and the second transistor, wherein a thickness of the first dielectric layer is greater than half the first distance, and a patterned metal layer formed on the first dielectric layer and partially covering the second gate.Type: ApplicationFiled: August 5, 2021Publication date: February 9, 2023Inventors: Chien-Hung Lin, Tsai-Hao Hung
-
Patent number: 11532499Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.Type: GrantFiled: February 23, 2021Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsai-Hao Hung, Ping-Cheng Ko, Tzu-Yang Lin, Fang-Yu Liu, Cheng-Han Wu
-
Publication number: 20220392945Abstract: A method is provided that includes forming a cavity in a substrate. The cavity is formed to extend into the substrate from a first surface to a second surface. Sidewall spacers are formed on sidewalls of the substrate in the cavity. A semiconductor layer is formed on the second surface in the cavity of the substrate, and the semiconductor layer abuts the sidewall spacers in the cavity.Type: ApplicationFiled: August 9, 2022Publication date: December 8, 2022Inventors: Tsai-Hao Hung, Tao-Cheng Liu, Ying-Hsun Chen