Patents by Inventor Tsai-Sheng Chen
Tsai-Sheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178002Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
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Publication number: 20240168373Abstract: A photoresist composition includes a mixture. The mixture includes a first photosensitive material and a second photosensitive material. The first photosensitive material is a 6-Sn oxide cluster, a 12-Sn oxide cluster or a combination thereof. The second photosensitive material has a composition being different from a composition of the first photosensitive material.Type: ApplicationFiled: June 13, 2023Publication date: May 23, 2024Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Tsing Hua UniversityInventors: Jui-Hsiung LIU, Tsai-Sheng GAU, Burn Jeng LIN, Yan-Ru WU, Ting-An LIN, Han-Tsung TSAI, Po-Hsiung CHEN
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Publication number: 20240111210Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.Type: ApplicationFiled: May 9, 2023Publication date: April 4, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Jui-Hsiung LIU, Pin-Chia LIAO, Ting-An LIN, Ting-An SHIH, Yu-Fang TSENG, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
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Publication number: 20240112912Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (Al) or formula (A2): Zr12O8(OH)14(RCO2)18??Formula (A1); or Hf6O4(OH)6(RCO2)10??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.Type: ApplicationFiled: July 28, 2023Publication date: April 4, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Jui-Hsiung LIU, Yu-Fang TSENG, Pin-Chia LIAO, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
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Publication number: 20240087960Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.Type: ApplicationFiled: November 13, 2023Publication date: March 14, 2024Inventors: Yu-Lien HUANG, Ching-Feng FU, Huan-Just LIN, Fu-Sheng LI, Tsai-Jung HO, Bor Chiuan HSIEH, Guan-Xuan CHEN, Guan-Ren WANG
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Publication number: 20240069878Abstract: Aspects of the present disclosure provide a method for training a predictor that predicts performance of a plurality of machine learning (ML) models on platforms. For example, the method can include converting each of the ML models into a plurality of instructions or the instructions and a plurality of intermediate representations (IRs). The method can also include simulating execution of the instructions corresponding to each of the ML models on a platform and generating instruction performance reports. Each of the instruction performance reports can be associated with performance of the instructions corresponding to one of the ML models that are executed on the platform. The method can also include training the predictor with the instructions or the IRs as learning features and the instruction performance reports as learning labels, compiling the predictor into a library file, and storing the library file in a storage device.Type: ApplicationFiled: July 3, 2023Publication date: February 29, 2024Applicant: MEDIATEK INC.Inventors: Huai-Ting LI, I-Lin CHEN, Tsai JEN CHIEH, Cheng-Sheng CHAN, ShengJe HUNG, Yi-Min TSAI, Huang YA-LIN
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Patent number: 11362464Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.Type: GrantFiled: September 22, 2020Date of Patent: June 14, 2022Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Patent number: 11316305Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.Type: GrantFiled: September 22, 2020Date of Patent: April 26, 2022Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Publication number: 20220052488Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.Type: ApplicationFiled: September 22, 2020Publication date: February 17, 2022Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Publication number: 20220052489Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.Type: ApplicationFiled: September 22, 2020Publication date: February 17, 2022Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Patent number: 10568200Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: GrantFiled: November 3, 2017Date of Patent: February 18, 2020Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
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Patent number: 10568198Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: GrantFiled: November 1, 2017Date of Patent: February 18, 2020Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
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Patent number: 10568199Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: GrantFiled: November 3, 2017Date of Patent: February 18, 2020Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
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Publication number: 20180376582Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: ApplicationFiled: November 1, 2017Publication date: December 27, 2018Inventors: Nai-Shung CHANG, Tsai-Sheng CHEN, Chang-Li TAN, Yun-Han CHEN, Hsiu-Wen HO
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Publication number: 20180374789Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: ApplicationFiled: November 3, 2017Publication date: December 27, 2018Inventors: Nai-Shung CHANG, Tsai-Sheng CHEN, Chang-Li TAN, Yun-Han CHEN, Hsiu-Wen HO
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Publication number: 20180374790Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: ApplicationFiled: November 3, 2017Publication date: December 27, 2018Inventors: Nai-Shung CHANG, Tsai-Sheng CHEN, Chang-Li TAN, Yun-Han CHEN, Hsiu-Wen HO
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Patent number: 9198286Abstract: A circuit board including a first patterned conductive layer and a second patterned conductive layer isolated from the first patterned conductive layer is provided. The first patterned conductive layer has first signal traces and first ground traces. The second patterned conductive layer has second signal traces and second ground traces. An orthogonal projection of the second ground trace on the first patterned conductive layer partially overlaps at least one of the first signal traces. An orthogonal projection of the first ground trace on the second patterned conductive layer partially overlaps at least one of the second signal traces. An electronic assembly including the afore-described circuit board and a chip package connected thereto is also provided.Type: GrantFiled: August 29, 2014Date of Patent: November 24, 2015Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Nai-Shung Chang, Yun-Han Chen, Chun-Yen Kang, Tsai-Sheng Chen
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Publication number: 20150195906Abstract: A circuit board including a first patterned conductive layer and a second patterned conductive layer isolated from the first patterned conductive layer is provided. The first patterned conductive layer has first signal traces and first ground traces. The second patterned conductive layer has second signal traces and second ground traces. An orthogonal projection of the second ground trace on the first patterned conductive layer partially overlaps at least one of the first signal traces. An orthogonal projection of the first ground trace on the second patterned conductive layer partially overlaps at least one of the second signal traces. An electronic assembly including the afore-described circuit board and a chip package connected thereto is also provided.Type: ApplicationFiled: August 29, 2014Publication date: July 9, 2015Inventors: Nai-Shung CHANG, Yun-Han CHEN, Chun-Yen KANG, Tsai-Sheng CHEN
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Patent number: 6981162Abstract: A suspend-to-RAM controlling circuit includes a RAM (random access memory) controller, a logic circuit and at least one RAM module. The RAM controller has a controlling pin connected to the logic circuit. Each of the RAM modules has a first enable pin and a second enable pin connected to output pins of the logic circuit. The RAM module is driven to the STR (suspend-to-RAM) state after receiving an STR signal from the logic circuit. Therefore, the RAM controller can provide STR signals to a plurality of RAM modules by only one controlling pin in incorporation with the logic circuit.Type: GrantFiled: May 29, 2002Date of Patent: December 27, 2005Assignee: Via Technologies, Inc.Inventors: Nai-Shung Chang, Tsai-Sheng Chen
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Layout structure for providing stable power source to a main bridge chip substrate and a motherboard
Publication number: 20050263849Abstract: This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.Type: ApplicationFiled: August 2, 2005Publication date: December 1, 2005Inventors: Nai-Shung Chang, Shu-Hui Chen, Tsai-Sheng Chen, Chia-Hsing Yu