Abstract: A processor has a clock generator circuit, a sleep pin that receives an external sleep signal, and a first interface circuit coupled to the clock generator circuit and the sleep pin. The clock generator circuit generates a core clock signal and a bus clock signal in response to an external clock signal. When the external sleep signal is asserted, the processor enters a sleep state when the core clock signal and the bus clock signal are in a first predetermined relationship with each other.

Abstract: A circuit dynamically sizes a bus transaction on a bus of a first size. The bus is formed by multiple signals. The circuit comprises a separator, a selecting element, and a combining element. The separator separates the bus signals into two groups of signals of a second size. The selecting element selects one of the two separated groups in response to a control signal indicating the data size of the bus transaction. The combining element combines a separated group of signals and a selected group of signals.

Abstract: A processor capable of selecting between a write-back and a write-through mode of operation includes a bus interface unit for transferring information across the external bus. A local cache memory is coupled to the bus interface unit for storing information received from the bus interface unit. The processor also includes a control unit coupled to the cache memory and the bus interface unit. The control unit is operable to restart an interrupted operation from a point of interruption. A storage device coupled to the control unit stores a value corresponding to the point of interruption of the operation.