Abstract: The present invention includes a CDR circuit including a phase detector, a neural network circuit, a controller and a clock signal generator is disclosed. The phase detector is configured to use a clock signal to sample an input signal to generate a plurality of phase detection results. The neural network circuit is coupled to the phase detector, and is configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal. The controller is configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal. The clock signal generator is configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.

Abstract: The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

Abstract: The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

Abstract: The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.

Abstract: The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.

Abstract: A clock data recovery apparatus includes an oscillator, a sampler circuit, and a frequency control circuit. The oscillator generates a clock signal according to a bias voltage. The sampler circuit samples an input data signal to generate a sampling signal according to the clock signal. The frequency control circuit generates the bias voltage by performing integration calculation, digital-to-analog conversion, and low-pass filtering for the sampling signal.

Abstract: A clock data recovery apparatus includes an oscillator, a sampler circuit, and a frequency control circuit. The oscillator generates a clock signal according to a bias voltage. The sampler circuit samples an input data signal to generate a sampling signal according to the clock signal. The frequency control circuit generates the bias voltage by performing integration calculation, digital-to-analog conversion, and low-pass filtering for the sampling signal.

Abstract: A phase lock loop apparatus is disclosed. The phase lock loop apparatus comprises a phase detecting module, a logic processing module, a charge pump and loop filter (CPLF), and a voltage control oscillator. The phase detecting module detects the phase difference between an input data signal and a clock signal to generate a first index signal. The logic processing module performs a high-frequency dithering process to the first index signal to generate a second index signal. The CPLF adjusts a control voltage according to the first index signal and the second index signal, and outputs the adjusted control voltage. The voltage control oscillator adjusts the frequency or phase of the clock signal and outputs the adjusted clock signal to the phase detecting module. The frequency of the second index signal is equal to or larger than the frequency of the first index signal.

Abstract: A phase lock loop apparatus is disclosed. The phase lock loop apparatus comprises a phase detecting module, a logic processing module, a charge pump and loop filter (CPLF), and a voltage control oscillator. The phase detecting module detects the phase difference between an input data signal and a clock signal to generate a first index signal. The logic processing module performs a high-frequency dithering process to the first index signal to generate a second index signal. The CPLF adjusts a control voltage according to the first index signal and the second index signal, and outputs the adjusted control voltage. The voltage control oscillator adjusts the frequency or phase of the clock signal and outputs the adjusted clock signal to the phase detecting module. The frequency of the second index signal is equal to or larger than the frequency of the first index signal.

Abstract: A phase lock loop device further includes a probability shaping device provided between a phase detection device and charge pump and loop filter (CPLF) device. The probability shaping device operates to reduce the frequency of outputting up-index or down-index; thereby shaping probability distribution to reduce degradation due to mismatching of the CPLF device.

Abstract: A sensing apparatus is disclosed. The sensing apparatus comprises a first image capturing module, a second image capturing module, a calculating module, and a controlling module. The first image capturing module and the second image capturing module capture a first image and a second image related to a plurality of objects respectively at a specific time. The calculating module obtains a 3-D position of an object according to the first image and the second image and obtains a 3-D displacement of the object according to the 3-D position and a former 3-D position of the object. If any one of 3-D displacements corresponding to the objects is approximately vertical, the controlling module controls an electrical apparatus to perform a first function. If a weighting average of approximately horizontal vector components of all 3-D displacements meets a condition, the controlling module controls the electrical apparatus to perform a second function.

Abstract: A clock data recovery circuit with feedback type phase discrimination. The clock data recovery circuit has an output signal of B bits and comprises a sampler, a phase region decision circuit, a phase status register and a multiplexer. The sampler oversamples k*B bits per cycle from a data input signal according to a sampling clock signal. The phase region decision circuit generates a plurality of binary up-down decision signals according to the oversampled data input signal and a current phase status signal. The phase status register generates the current phase status signal according to the binary up-down decision signals. The multiplexer selects data of B bits from the oversampled data input signal according to the current phase status signal.

Abstract: A method for compensating a baseline wander of a transmission signal and related circuit are provided. The transmission signal includes a plurality of first pulses and a plurality of second pulses for representing digital data coded in the transmission signal. The method includes generating an accumulation result according to a number of the first pulses and a number of the second pulses for estimating the baseline wander of the transmission signal, and compensating the baseline wander of the transmission line according to the accumulation result.

Abstract: A phase lock loop device further includes a probability shaping device provided between a phase detection device and charge pump and loop filter (CPLF) device. The probability shaping device operates to reduce the frequency of outputting up-index or down-index; thereby shaping probability distribution to reduce degradation due to mismatching of the CPLF device.

Abstract: A circuit of the present invention applied for the PLL is disclosed. The circuit comprises a loop filter, a first charge pump, and a second charge pump. The loop filter includes a unit gain buffer, a first capacitor connected to the input terminal of the unit gain buffer and a ground, a second capacitor connected to the output terminal of the unit gain buffer and the ground, and a low pass filter consisting of a resistor and a third capacitor connected to the output terminal of the unit gain buffer. The first charge pump is coupled to the output terminal of the RC low pass filter, and the second charge pump coupled to the input terminal of the unit gain buffer in the loop filter. The second capacitor in loop filter circuit of the present invention and the improvement on the charge pump are improved the stability of the PPL and reduced the influence of the loop filter circuit by the unit gain buffer.

Abstract: A clock data recovery circuit with feedback type phase discrimination. The clock data recovery circuit has an output signal of B bits and comprises a sampler, a phase region decision circuit, a phase status register and a multiplexer. The sampler oversamples k*B bits per cycle from a data input signal according to a sampling clock signal. The phase region decision circuit generates a plurality of binary up-down decision signals according to the oversampled data input signal and a current phase status signal. The phase status register generates the current phase status signal according to the binary up-down decision signals. The multiplexer selects data of B bits from the oversampled data input signal according to the current phase status signal.

Abstract: A method for compensating a baseline wander of a transmission signal and related circuit are provided. The transmission signal includes a plurality of first pulses and a plurality of second pulses for representing digital data coded in the transmission signal. The method includes generating an accumulation result according to a number of the first pulses and a number of the second pulses for estimating the baseline wander of the transmission signal, and compensating the baseline wander of the transmission line according to the accumulation result.