Abstract: A charging circuit for a capacitor includes a current mirror module including a first branch circuit, a second branch circuit and a third branch circuit for supplying a plurality of output currents respectively, a switching module coupled to the first branch circuit and the second branch circuit for determining a conducting condition of the switching module according to the plurality of output currents from the first branch circuit and the second branch circuit, and an active loading circuit coupled to the third branch circuit and the switching module for adjusting a current passing through the active loading circuit according to the conducting condition of the switching module. The capacitor has one end coupled to the first branch circuit and the switching module to process a charging operation according to the output current of the first branch circuit.

Abstract: A current-limit system for limiting an average current of an output signal of a DC-DC converter includes a current sensing device, coupled to the DC-DC converter, for detecting the average current of the output signal of the DC-DC converter; and a current-to-voltage converting module, coupled to the current sensing device, for converting the average current into a clamp voltage, in order to control the DC-DC converter according to the clamp voltage.

Abstract: A current-limit system for limiting an average current of an output signal of a DC-DC converter includes a current sensing device, coupled to the DC-DC converter, for detecting the average current of the output signal of the DC-DC converter; and a current-to-voltage converting module, coupled to the current sensing device, for converting the average current into a clamp voltage, in order to control the DC-DC converter according to the clamp voltage.

Abstract: A charging circuit for a capacitor includes a current mirror module including a first branch circuit, a second branch circuit and a third branch circuit for supplying a plurality of output currents respectively, a switching module coupled to the first branch circuit and the second branch circuit for determining a conducting condition of the switching module according to the plurality of output currents from the first branch circuit and the second branch circuit, and an active loading circuit coupled to the third branch circuit and the switching module for adjusting a current passing through the active loading circuit according to the conducting condition of the switching module. The capacitor has one end coupled to the first branch circuit and the switching module to process a charging operation according to the output current of the first branch circuit.

Abstract: A switch circuit capable of preventing voltage spike, includes an input end for receiving an input voltage, an output end for outputting an output voltage, a switch unit for controlling an electrical connection between the input end and the output end according to a control signal, a protection unit for generating the control signal according to an input current passing through the input end, and a first parasitic transistor for controlling an electrical connection between a second end and a third end according to the control signal, wherein when the input current is greater than a threshold value, the switch unit turns off electrical connection between the input end and the output end according to the control signal, and the first parasitic transistor turns on electrical connection between the second end and the third end of first parasitic transistor according to the control signal to reduce variation of input current.

Abstract: A power MOS device having a gate with crosshatched lattice pattern on a substrate and at lease a source or a drain isolated by the gate, characterized in that the source has only one diffusion region of a pre-selected conductivity type. According to one embodiment, the source has a source diffusion of first conductivity type and the drain has a drain diffusion of first conductivity type. The source diffusion is replaced with substrate contact diffusion at some source sites across the transistor array.