Patents by Inventor Tse Ming Chu

Tse Ming Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8937386
    Abstract: The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: January 20, 2015
    Assignee: Aflash Technology Co., Ltd.
    Inventors: Tse-Ming Chu, Sung-Chuan Ma
  • Patent number: 8299629
    Abstract: A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: October 30, 2012
    Assignee: Aflash Technology Co., Ltd.
    Inventors: Kuei-Wu Chu, Tse Ming Chu
  • Publication number: 20120196438
    Abstract: The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.
    Type: Application
    Filed: March 7, 2012
    Publication date: August 2, 2012
    Inventors: Tse-Ming CHU, Sung-Chuan Ma
  • Publication number: 20120074558
    Abstract: A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications.
    Type: Application
    Filed: March 7, 2011
    Publication date: March 29, 2012
    Applicant: MAO BANG ELECTRONIC CO., LTD.
    Inventors: Hsuan Yu LU, Tse Ming CHU, Kuei-Wu CHU
  • Publication number: 20110260300
    Abstract: A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 27, 2011
    Applicant: MAO BANG ELECTRONIC CO., LTD.
    Inventors: Kuei-Wu Chu, Tse Ming Chu
  • Publication number: 20110176021
    Abstract: An image-processing integrated circuit includes an image-processing die, a conductive layer, first optical units and a second optical unit. The conductive layer is provided on a face of the image-processing die. The first optical units are provided on an opposite face of the image-processing die. The second optical unit is provided on the first optical units.
    Type: Application
    Filed: October 20, 2010
    Publication date: July 21, 2011
    Applicant: MAO BANG ELECTRONIC CO., LTD.
    Inventors: Tse Ming Chu, Ma Sung Chuan
  • Publication number: 20110143536
    Abstract: Disclosed is a method for making an aperture in a carrier and electrically connecting two opposite faces of the carrier. At first, a carrier is provided. Secondly, a heater is provided for heating a portion of the carrier in an environment rich in oxygen, thus making an aperture in the carrier and forming an isolative layer on the wall of the aperture synchronously. Finally, the aperture is filled with a conductive material.
    Type: Application
    Filed: October 20, 2010
    Publication date: June 16, 2011
    Applicant: MAO BANG ELECTRONIC CO., LTD.
    Inventor: Tse Ming Chu
  • Publication number: 20110031635
    Abstract: A device having stacked integrated circuit (IC) chips is provided. The chips and other wires are connected through circuit contacts and notches or apertures. The notches or apertures are filled with a conductive material. Thus, flexibility of circuit layout is achieved with easy fabrication and enhanced reliability.
    Type: Application
    Filed: October 20, 2010
    Publication date: February 10, 2011
    Applicant: MAO BANG ELECTRONIC CO., LTD.
    Inventors: Tse Ming Chu, Sung Chuan MA
  • Publication number: 20100244200
    Abstract: A wafer has a cutting part filled with a connecting medium. After the wafer is cut into chips along the cutting part, two contacts on two surfaces of the chip can be connected through corresponding leading wires and the connecting medium. Thus, the chip can have a flexible layout.
    Type: Application
    Filed: July 24, 2007
    Publication date: September 30, 2010
    Applicants: Chu, Tse Ming, Ma, Sung Chuan
    Inventors: Tse Ming Chu, Sung Chuan Ma
  • Publication number: 20100133686
    Abstract: A chip package includes a die, a pad-mounting surface on the die, a plurality of bonding pad arranged at the pad-mounting surface, at least one dielectric layer cover over the pad-mounting surface, and at least one conductive wire set in the dielectric layer. The formation of the conductive wire consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire.
    Type: Application
    Filed: December 1, 2009
    Publication date: June 3, 2010
    Inventors: Tse-Ming CHU, Sung-Chuan MA