Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.

Abstract: A silicon oxide layer is formed on a semiconductor wafer by performing a high temperature oxidation (HTO) process using dichlorosilane (SiH2Cl2) and nitrous oxide (N2O), as reacting gases, having a flow rates with a ratio greater than 2:1, respectively. The reacting moles of dichlorosilane to nitrous oxide are in the proportion of 1:2.

Abstract: A silicon oxide layer is formed on a semiconductor wafer by performing a high temperature oxidation (HTO) process using dichlorosilane (SiH2Cl2) and nitrous oxide (N2O), as reacting gases, having a flow rates with a ratio greater than 2:1, respectively. The reacting moles of dichlorosilane to nitrous oxide are in the proportion of 1:2.

Abstract: A method of increasing the selectivity of silicon nitride deposition. A substrate is provided. A silicon oxide layer is formed over a portion of the substrate. Ammonia NH3 is passed over the silicon oxide layer and the substrate surface for a definite period to perform a surface treatment. Silicon nitride is subsequently deposited over the substrate and the silicon oxide layer.

Abstract: The present invention provides a method of fabricating capacitor dielectric layer. A bottom electrode covered by a native oxide layer on a chip is provided. The chip is disposed into a low pressure furnace. A mixture of dichlorosilane and ammonia is introduced into the low pressure furnace to form a nitride layer on the native oxide layer. In the same low pressure furnace, nitrogen monoxide or nitric oxygen is infused to form an oxynitride layer on the nitride layer.

Abstract: A method for cleaning a semiconductor wafer which includes the sequential steps of cleaning the wafer in a dilute hydrofluoric acid bath, cleaning the wafer in a first ozone bath, cleaning the wafer in a dilute hydrofluoric acid/hydrogen peroxide/hydrogen chloride bath, followed by cleaning the wafer in a second ozone bath. The method uses the dilute hydrofluoric acid/hydrogen peroxide/hydrochloric acid bath instead of the conventional DHF bath and RCA2 bath. Hence, the amount of chemicals consumed and the number of baths used by the cleaning station are lowered. In addition, ozone is passed into an overflow loath so that the highly reactive ozone can be utilized to clean the wafer without putting additional load on the cleaning station. Therefore, the cleaning operation can be carried out in a smaller cleaning station using somewhat lower temperature and lower concentration chemical solutions. The efficiency is as high as a multi-bath station, but chemicals are not wasted.

Abstract: A method of water mark inspection. By forming a pattern on a test wafer, the water mark formed thereon directly reflects the features of a wafer product to be evaluated. The water mark is formed by simulating fabrication process conditions of forming the wafer product of which the performance is to be evaluated. Thus, after scanning the water mark by a defect inspection machine, the performance of the wafer product is evaluated.