Abstract: The present disclosure provides a semiconductor structure including a substrate, a bottom gate portion disposed in the substrate, a top gate portion stacked over the bottom gate portion, a first channel layer sandwiched between the top gate portion and the bottom gate portion, and a source/drain region disposed in the substrate at two opposite sides of the top gate portion.

Abstract: A semiconductor structure includes a substrate including a surface, a first doped region and a second doped region, wherein the first doped region and the second doped region are disposed under the surface; a gate structure disposed between the first doped region and the second doped region; a capacitor disposed over and electrically connected to the first doped region; and a bit line disposed over and electrically connected to the second doped region, wherein the bit line includes a conductive portion and an insulating portion surrounding the conductive portion, and the insulating portion includes ferroelectric material.

Abstract: A semiconductor device includes a substrate, at least one trench, an insulating layer, a lower metal layer, a negative capacitance material layer, and an upper metal layer. The trench has an inner surface in the substrate. The insulating layer is disposed on and lining the inner surface of the trench. The lower metal layer is disposed on the insulating layer and partially filling the trench. The negative capacitance material layer is disposed on and lining the insulating layer and the lower metal layer, in which a remained portion of the trench is defined by the negative capacitance material layer. The upper metal layer is disposed on the negative capacitance material layer and filling the remained portion of the trench.

Abstract: A memory device includes a substrate, a first gate structure, and a first oxide layer. The substrate has a first protruding portion and a second protruding portion adjacent to the first protruding portion. The first gate structure is on the substrate and between the first and second protruding portions. The first oxide layer is disposed between the substrate and the first gate structure, and includes a first portion and a second portion. The first portion is between the first gate structure and the first protruding portion, the second portion is between the first gate structure and the second protruding portion, and a thickness of the first portion is greater than a thickness of the second portion.

Abstract: A memory structure includes a first memory cell, a first word line and a second word line. The first word line includes a first portion, a second portion and a third portion. The first portion extends from an end of the second portion along a first direction, and the third portion extends from an another end of the second portion along a second direction. An angle between the first direction and the second direction is less than 180°. The second word line includes a forth portion, a fifth portion and a sixth portion. The forth portion extends from an end of the fifth portion along a third direction, and the sixth portion extends from an another end of the fifth portion along a forth direction. An angle between the third direction and the forth direction is less than 180°.

Abstract: The semiconductor layout structure includes an active region surrounded by an isolation structure, at least one first gate structure disposed over the active region and the isolation structure, at least one second gate structure disposed over the active region and the isolation structure, and a plurality of source/drain regions disposed in the active region. The active region includes two first regions, a second region disposed between the two first regions, a third region disposed between one of the first region and the second region, and a fourth region disposed between the other first region and the second region.

Abstract: A memory structure includes a first memory cell, a first word line and a second word line. The first word line includes a first portion, a second portion and a third portion. The first portion extends from an end of the second portion along a first direction, and the third portion extends from an another end of the second portion along a second direction. An angle between the first direction and the second direction is less than 180°. The second word line includes a forth portion, a fifth portion and a sixth portion. The forth portion extends from an end of the fifth portion along a third direction, and the sixth portion extends from an another end of the fifth portion along a forth direction. An angle between the third direction and the forth direction is less than 180°.

Abstract: A semiconductor structure includes a silicon control rectifier (SCR) region and a NPN region adjacent to the SCR region. The silicon control rectifier (SCR) region includes a first p-well region, a first n-well region surrounded by the first p-well region and a first P+ region in the first p-well region and spaced apart from the first n-well region. The NPN region includes a second p-well region, a first N+ region, a second N+ region and a second P+ region. The first N+ region is coupled to the second p-well region and an electrostatic discharge source. The second N+ region is coupled to the second p-well region and spaced apart from the first N+ region. The second P+ region is disposed in the second p-well region and equipotentially connected to the first P+ region in the first p-well region.

Abstract: The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.

Abstract: The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first conductivity type, a gate formed on the substrate, a source region and a drain region formed in the substrate, and a body region formed in the substrate. The substrate and the body region include a first conductivity type. The source region and the drain region include a second conductivity type. And the first conductivity type and the second conductivity type are complementary to each other. The body region is electrically connected to the gate.

Abstract: The present disclosure provides a transistor device and a semiconductor layout structure. The transistor device includes an active region disposed in a substrate, a gate structure disposed over the active region, and a source/drain region disposed at two opposite sides of the gate structure. The active region includes a first region including a first length, a second region including a second length less than the first length, and a third region between the first region and the second region. The gate structure includes a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction. The first portion is disposed over at least the third region of the active region, and the second portion is disposed over at least a portion of the third region and a portion of the second region.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.

Abstract: The present disclosure provides a diode structure and an electrostatic discharge (ESD) protection circuit including the same. The diode structure includes a P-type substrate. The diode structure further includes a plurality of wavy N-doping regions formed on the P-type substrate. Each of the wavy N-doping regions extends in a first direction and has an N-doping width in a second direction perpendicular to the first direction. The diode structure further includes a plurality of wavy P-doping regions formed on the P-type substrate. Each of the wavy P-doping regions extends in the first direction and has a P-doping width in the second direction. The N-doping widths are essentially identical at different positions along the first direction, and the P-doping widths are essentially identical at different positions along the first direction.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.

Abstract: The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.

Abstract: The present disclosure provides a semiconductor structure including a substrate, a bottom gate portion disposed in the substrate, a top gate portion stacked over the bottom gate portion, a first channel layer sandwiched between the top gate portion and the bottom gate portion, and a source/drain region disposed in the substrate at two opposite sides of the top gate portion.

Abstract: The present disclosure provides a diode structure and an electrostatic discharge (ESD) protection circuit including the same. The diode structure includes a P-type substrate. The diode structure further includes a plurality of wavy N-doping regions formed on the P-type substrate. Each of the wavy N-doping regions extends in a first direction and has an N-doping width in a second direction perpendicular to the first direction. The diode structure further includes a plurality of wavy P-doping regions formed on the P-type substrate. Each of the wavy P-doping regions extends in the first direction and has a P-doping width in the second direction. The N-doping widths are essentially identical at different positions along the first direction, and the P-doping widths are essentially identical at different positions along the first direction.

Abstract: The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.

Abstract: The present disclosure provides a transistor device and a semiconductor layout structure. The transistor device includes an active region disposed in a substrate, a gate structure disposed over the active region, and a source/drain region disposed at two opposite sides of the gate structure. The active region includes a first region including a first length, a second region including a second length less than the first length, and a third region between the first region and the second region. The gate structure includes a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction. The first portion is disposed over at least the third region of the active region, and the second portion is disposed over at least a portion of the third region and a portion of the second region.