Abstract: A computer system consists of a plurality of electronic elements and a switch control circuit. The switch control circuit controls the computer system to enter a stand-by/power off state from a normal state when the computer system receives a stand-by/power off command under the normal state, and stops outputting a stand-by power having at least one stand-by voltage level to at least one part of electronic elements among the plurality of electronic elements. At this time, the computer system has entered a simulated mechanical off state from the stand-by/power off state. A number of electronic elements supplied by the stand-by power when the computer system lies under the simulated mechanical off state is smaller than a number of electronic elements supplied by the stand-by power when the computer system lies under the stand-by/power off state.

Abstract: A controlling circuit for controlling an operating clock of a logic circuit in an electronic device and the method thereof are disclosed. The controlling circuit includes a storage device, a detector, at least one comparator, and a controller. The storage device stores a first threshold value and a first return value. The detector detects a system load of the electronic device to generate a detection value. The comparator compares the detection value with the first threshold value or the first return value. When the detection value decreases to reach the first threshold value, the comparator generates a first indication signal. When the detection value increase to reach the first return value, the comparator generates a second indication signal. The controller enables underclocking of the logic circuit when receiving the first indication signal, and disables underclocking of the logic circuit when receiving the second indication signal.

Abstract: A pulse width modulation (PWM) controlling module, includes: a PWM controller, a load detector, and an adjusting module. The PWM controller generates a PWM signal that is utilized for controlling a supply voltage applied to an electronic system. The load detector, coupled to the PWM controller, detects a load of the electronic system according to the PWM signal and generates a decision value accordingly. The adjusting module, coupled to the PWM controller and the load detector, controls the PWM controller to adjust the PWM signal according to the decision value.

Abstract: A pulse width modulation (PWM) controlling module, includes: a PWM controller, a load detector, and an adjusting module. The PWM controller generates a PWM signal that is utilized for controlling a supply voltage applied to an electronic system. The load detector, coupled to the PWM controller, detects a load of the electronic system according to the PWM signal and generates a decision value accordingly. The adjusting module, coupled to the PWM controller and the load detector, controls the PWM controller to adjust the PWM signal according to the decision value.

Abstract: The present invention provides a method for providing an auxiliary basic input/output system (BIOS) code in a computer system, where the computer system includes a central processing unit (CPU) for executing an operation system (OS) program. The method comprises: providing a main BIOS memory for storing a main BIOS code to be executed in a main mode; providing an auxiliary BIOS memory for storing the auxiliary BIOS code to be executed in an auxiliary mode; and in the main mode, if a specific time interval expires and the OS program is not successfully executed, disabling the main BIOS code, enabling the auxiliary BIOS code, and resetting the computer system to switch from the main mode to the auxiliary mode.

Abstract: A controlling circuit for controlling an operating clock of a logic circuit in an electronic device and the method thereof are disclosed. The controlling circuit includes a storage device, a detector, at least one comparator, and a controller. The storage device stores a first threshold value and a first return value. The detector detects a system load of the electronic device to generate a detection value. The comparator compares the detection value with the first threshold value or the first return value. When the detection value decreases to reach the first threshold value, the comparator generates a first indication signal. When the detection value increase to reach the first return value, the comparator generates a second indication signal. The controller enables underclocking of the logic circuit when receiving the first indication signal, and disables underclocking of the logic circuit when receiving the second indication signal.

Abstract: A method for detecting a power load of a power supply module, includes: receiving a pulse width modulation (PWM) signal generated by the power supply module, wherein the PWM signal is utilized for controlling a driving voltage outputted from the power supply module; detecting a duty cycle of the PWM signal; and determining the power load of the power supply module according to the duty cycle.

Abstract: A method for detecting a power load of a power supply module, includes: receiving a pulse width modulation (PWM) signal generated by the power supply module, wherein the PWM signal is utilized for controlling a driving voltage outputted from the power supply module; detecting a duty cycle of the PWM signal; and determining the power load of the power supply module according to the duty cycle.

Abstract: A computing apparatus includes a mainboard, a small outline dual in-line memory module (SO-DIMM) compliant slot, and a hardware management add-on card. The mainboard has electronic components mounted thereon. The SO-DIMM compliant slot is mounted on the mainboard and has a set of first electrical contacts coupled to the electronic components. The hardware management add-on card is mounted removably on the SO-DIMM compliant slot, has a set of second electrical contacts for connecting electrically with the first electrical contacts, and is operable so as to enable monitoring of the electronic components.

Abstract: A solution for maintaining the wake-up functions of a computer after a power loss is provided. To reset parameters relating to the wake-up functions, the computer is automatically turned on when the power is supplied again. Then, the computer is forced to be power-off by an output signal to switch the computer system to a state capable of executing the wake-up functions.