Patents by Inventor Tsu-Hui SU
Tsu-Hui SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11923437Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.Type: GrantFiled: October 25, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
-
Publication number: 20240047545Abstract: Fin and nanostructured channel structure formation techniques for three-dimensional transistors can tune device performance. For example, fin profile control can be achieved by modifying the shape of fins/nanostructured channel structures so as to reduce their line edge roughness. Consequently, current flow within the channel regions of fins and nanostructured channel structures can be improved, enhancing device performance.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ssu-Yu Liao, Ta-Wei Lin, Tsu-Hui Su, Chun-Hsiang Fan, Chun-Hsiang Fan, Kuo-Bin Huang
-
Publication number: 20230387263Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.Type: ApplicationFiled: July 28, 2023Publication date: November 30, 2023Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
-
Publication number: 20230147848Abstract: A method includes depositing a silicon layer over a semiconductor region, forming dielectric isolation regions extending into the silicon layer and the semiconductor region, and recessing the dielectric isolation regions. A first portion of the silicon layer and a second portion of the semiconductor region are between the dielectric isolation regions, and protrude higher than top surfaces of the dielectric isolation regions to form a semiconductor fin. The semiconductor fin is thinned, and after the first semiconductor fin is thinned, the first portion of the silicon layer remains. A gate stack is formed on the semiconductor fin.Type: ApplicationFiled: January 6, 2023Publication date: May 11, 2023Inventors: Tsu-Hui Su, Ssu-Yu Liao, Chun-Hsiang Fan, Kuo-Bin Huang
-
Publication number: 20220359734Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Ssu-Yu Liao, Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
-
Patent number: 11424347Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.Type: GrantFiled: June 11, 2020Date of Patent: August 23, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ssu-Yu Liao, Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
-
Publication number: 20220045199Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.Type: ApplicationFiled: October 25, 2021Publication date: February 10, 2022Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
-
Publication number: 20210391449Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.Type: ApplicationFiled: June 11, 2020Publication date: December 16, 2021Inventors: Ssu-Yu Liao, Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
-
Patent number: 11158726Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.Type: GrantFiled: July 31, 2019Date of Patent: October 26, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
-
Publication number: 20210036130Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.Type: ApplicationFiled: July 31, 2019Publication date: February 4, 2021Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
-
Patent number: 10777649Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.Type: GrantFiled: March 20, 2017Date of Patent: September 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsu-Hui Su, Chih-Ming Chen, Chia-Shiung Tsai, Chung-Yi Yu, Szu-Yu Wang
-
Patent number: 10497560Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution.Type: GrantFiled: April 25, 2014Date of Patent: December 3, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ming Chen, Tsu-Hui Su, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
-
Patent number: 9929007Abstract: The present disclosure relates to a structure and method for reducing dangling bonds around quantum dots in a memory cell. In some embodiments, the structure has a semiconductor substrate having a tunnel dielectric layer disposed over it and a plurality of quantum dots disposed over the tunnel dielectric layer. A passivation layer is formed conformally over outer surfaces of the quantum dots and a top dielectric layer is disposed conformally around the passivation layer. The passivation layer can be formed prior to forming the top dielectric layer over the quantum dots or after forming the top dielectric layer. The passivation layer reduces the dangling bonds at an interface between the quantum dots and the top dielectric layer, thereby preventing trap sites that may hinder operations of the memory cell.Type: GrantFiled: December 26, 2014Date of Patent: March 27, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ming Chen, Tsu-Hui Su, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai
-
Publication number: 20170194445Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.Type: ApplicationFiled: March 20, 2017Publication date: July 6, 2017Inventors: Tsu-Hui Su, Chih-Ming Chen, Chia-Shiung Tsai, Chung-Yi Yu, Szu-Yu Wang
-
Patent number: 9634105Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.Type: GrantFiled: January 14, 2015Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsu-Hui Su, Chih-Ming Chen, Chia-Shiung Tsai, Chung-Yi Yu, Szu-Yu Wang
-
Patent number: 9577077Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a first tunnel oxide is formed over a semiconductor substrate. A self-assembled monolayer (SAM) is then formed on the first tunnel oxide. The SAM includes spherical or spherical-like crystalline silicon dots having respective diameters which are less than approximately 30 nm. A second tunnel oxide is then formed over the SAM.Type: GrantFiled: June 19, 2014Date of Patent: February 21, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsu-Hui Su, Chih-Ming Chen, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai
-
Patent number: 9401434Abstract: The present disclosure relates to a structure and method for forming a flash memory cell with an improved erase speed and erase current. Si dots are used for charge trapping and an ONO sandwich structure is formed over the Si dots. Erase operation includes direct tunneling as well as FN tunneling which helps increase erase speed without compensating data retention.Type: GrantFiled: September 18, 2014Date of Patent: July 26, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ming Chen, Tsu-Hui Su, Szu-Yu Wang, Chung-Yi Yu
-
Publication number: 20160204212Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.Type: ApplicationFiled: January 14, 2015Publication date: July 14, 2016Inventors: Tsu-Hui Su, Chih-Ming Chen, Chia-Shiung Tsai, Chung-Yi Yu, Szu-Yu Wang
-
Publication number: 20160190349Abstract: The present disclosure relates to a structure and method for reducing dangling bonds around quantum dots in a memory cell. In some embodiments, the structure has a semiconductor substrate having a tunnel dielectric layer disposed over it and a plurality of quantum dots disposed over the tunnel dielectric layer. A passivation layer is formed conformally over outer surfaces of the quantum dots and a top dielectric layer is disposed conformally around the passivation layer. The passivation layer can be formed prior to forming the top dielectric layer over the quantum dots or after forming the top dielectric layer. The passivation layer reduces the dangling bonds at an interface between the quantum dots and the top dielectric layer, thereby preventing trap sites that may hinder operations of the memory cell.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: Chih-Ming Chen, Tsu-Hui Su, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai
-
Publication number: 20160087106Abstract: The present disclosure relates to a structure and method for forming a flash memory cell with an improved erase speed and erase current. Si dots are used for charge trapping and an ONO sandwich structure is formed over the Si dots. Erase operation includes direct tunneling as well as FN tunneling which helps increase erase speed without compensating data retention.Type: ApplicationFiled: September 18, 2014Publication date: March 24, 2016Inventors: Chih-Ming Chen, Tsu-Hui Su, Szu-Yu Wang, Chung-Yi Yu