Patents by Inventor Tsubasa Imamura
Tsubasa Imamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230307520Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming an electrode layer on a film containing indium and etching portions of the electrode layer left exposed by a mask layer until at least a portion of the film is exposed. A spacer film is formed to cover an upper surface of the electrode layer, side surfaces of the electrode layer, and an exposed upper surface of the film. The spacer film on the upper surface of the electrode layer and the exposed upper surface of the film is removed while leaving the spacer film on the side surfaces of the electrode layer. The exposed upper surface of the film is exposed to a reductive gas plasma to reduce portions of the film. These reduced portions of the film are then etched with a chemical solution.Type: ApplicationFiled: August 29, 2022Publication date: September 28, 2023Inventors: Takuya KIKUCHI, Yuya NAGATA, Masaya TODA, Kappei IMAMURA, Tsubasa IMAMURA
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Publication number: 20230274942Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes placing a substrate having a to-be-processed layer on a stage within an etching chamber and supplying an etching gas into the etching chamber while keeping the stage at a first temperature to perform an etching treatment to etch the to-be-processed layer on the substrate by using a reactive ion etching method. After the etching treatment, and without exposing the substrate to the atmosphere, supplying an inert gas into the etching chamber while keeping the stage at a second temperature, which is higher than the first temperature, to perform a high-temperature treatment to heat the to-be-processed layer.Type: ApplicationFiled: September 2, 2022Publication date: August 31, 2023Inventors: Hiroshi NAMBU, Junichi HASHIMOTO, Tsubasa IMAMURA
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Patent number: 11651969Abstract: An etching method according to one embodiment, includes alternately switching a first step and a second step. The first step introduces a first gas containing a fluorine atom without supplying radiofrequency voltage to form a surface layer on a surface of a target cooled at a temperature equal to or lower than a liquefaction temperature of the first gas. The second step introduces a second gas gaseous at the first temperature and different from the first gas, and supplies the radiofrequency voltage, to generate plasma from the second gas to etch the target by sputtering using the plasma.Type: GrantFiled: March 16, 2020Date of Patent: May 16, 2023Assignee: Kioxia CorporationInventors: Chihiro Abe, Toshiyuki Sasaki, Hisataka Hayashi, Mitsuhiro Omura, Tsubasa Imamura
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Publication number: 20230114349Abstract: An etching method according to one embodiment, includes alternately switching a first step and a second step. The first step introduces a first gas containing a fluorine atom without supplying radiofrequency voltage to form a surface layer on a surface of a target cooled at a temperature equal to or lower than a liquefaction temperature of the first gas. The second step introduces a second gas gaseous at the first temperature and different from the first gas, and supplies the radiofrequency voltage, to generate plasma from the second gas to etch the target by sputtering using the plasma.Type: ApplicationFiled: December 14, 2022Publication date: April 13, 2023Applicant: Kioxia CorporationInventors: Chihiro ABE, Toshiyuki SASAKI, Hisataka HAYASHI, Mitsuhiro OMURA, Tsubasa IMAMURA
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Publication number: 20220406611Abstract: A method for manufacturing a semiconductor device according to an embodiment is a method for manufacturing a semiconductor device including performing a first etching process of forming a recess in a layer to be processed formed on a substrate by reactive ion etching using a first gas, performing a first process of supplying hydrogen radicals to the recess by using a second gas containing hydrogen in a state where a temperature of the substrate is equal to or more than 200° C. and equal to or less than 350° C. after the first etching process, and performing a second etching process of etching a bottom surface of the recess by reactive ion etching using a third gas after the first process.Type: ApplicationFiled: December 9, 2021Publication date: December 22, 2022Applicant: Kioxia CorporationInventors: Atsushi TAKAHASHI, Tsubasa IMAMURA, Wu LI, Yuto ITAGAKI, Minki CHOU
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Publication number: 20220399222Abstract: A semiconductor device manufacturing apparatus according to an embodiment includes: a chamber; a holder provided in the chamber and capable of adsorbing a substrate, the holder including a recess on a surface, a first hole provided in the recess, and a second hole provided in the recess; a first gas passage connected to the first hole; a second gas passage connected to the second hole; a first valve provided in the first gas passage; a second valve provided in the second gas passage; a first gas supply pipe for supplying a first gas to the recess; and a gas discharge pipe for discharging a gas from the recess. The first gas passage and the second gas passage are connected to the first gas supply pipe, or the first gas passage and the second gas passage are connected to the gas discharge pipe.Type: ApplicationFiled: March 14, 2022Publication date: December 15, 2022Applicant: Kioxia CorporationInventors: Wu LI, Tsubasa IMAMURA, Yuto ITAGAKI, Minki CHOU
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Publication number: 20220077183Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of electrode layers provided separately from each other in a first direction perpendicular to a surface of the substrate. The device further includes a first insulator, a charge storage layer, a second insulator, a first semiconductor region including silicon, and a second semiconductor region including silicon and carbon, which are provided in order on side faces of the electrode layers, wherein an interface between the first semiconductor region and the second insulator includes fluorine.Type: ApplicationFiled: March 10, 2021Publication date: March 10, 2022Applicant: Kioxia CorporationInventors: Takaumi MORITA, Hisashi OKUCHI, Keiichi SAWA, Hiroyuki YAMASHITA, Toshiaki YANASE, Tsubasa IMAMURA
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Patent number: 11024510Abstract: According to one embodiment, a pattern forming method includes forming an organic layer on a first layer. The organic layer has a first region having a first thickness and a first width, a second region having a second thickness and a second width, and a third region located between the first region and the second region. The third region has a third thickness less than each of the first thickness and the second thickness and a third width. A second layer containing silicon oxide is then formed on a surface of the organic layer in a process chamber of a reactive ion etching device. The third region is then etched in the process chamber using the second layer as a mask.Type: GrantFiled: February 26, 2020Date of Patent: June 1, 2021Assignee: KIOXIA CORPORATIONInventor: Tsubasa Imamura
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Publication number: 20210090893Abstract: According to one embodiment, a pattern forming method includes forming an organic layer on a first layer. The organic layer has a first region having a first thickness and a first width, a second region having a second thickness and a second width, and a third region located between the first region and the second region. The third region has a third thickness less than each of the first thickness and the second thickness and a third width. A second layer containing silicon oxide is then formed on a surface of the organic layer in a process chamber of a reactive ion etching device. The third region is then etched in the process chamber using the second layer as a mask.Type: ApplicationFiled: February 26, 2020Publication date: March 25, 2021Inventor: Tsubasa IMAMURA
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Publication number: 20210020450Abstract: An etching method according to one embodiment, includes alternately switching a first step and a second step. The first step introduces a first gas containing a fluorine atom without supplying radiofrequency voltage to form a surface layer on a surface of a target cooled at a temperature equal to or lower than a liquefaction temperature of the first gas. The second step introduces a second gas gaseous at the first temperature and different from the first gas, and supplies the radiofrequency voltage, to generate plasma from the second gas to etch the target by sputtering using the plasma.Type: ApplicationFiled: March 16, 2020Publication date: January 21, 2021Applicant: Kioxia CorporationInventors: Chihiro ABE, Toshiyuki Sasaki, Hisataka Hayashi, Mitsuhiro Omura, Tsubasa Imamura
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Patent number: 10727278Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a first substrate. The method further includes performing a first process of processing a portion of the first film with plasma of first gas and a second process of removing the portion of the first film with plasma of second gas after the first process.Type: GrantFiled: September 6, 2018Date of Patent: July 28, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Tsubasa Imamura
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Patent number: 10490415Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The method further includes simultaneously flowing a first gas with a second gas containing a metal element to form a first opening in the second film and forming a third film containing the metal element on a side surface of the first opening. The method further includes forming a second opening in the first film below the first opening using the second film as a mask.Type: GrantFiled: August 31, 2016Date of Patent: November 26, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsubasa Imamura, Atsushi Takahashi, Toshiyuki Sasaki
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Publication number: 20190288035Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a first substrate. The method further includes performing a first process of processing a portion of the first film with plasma of first gas and a second process of removing the portion of the first film with plasma of second gas after the first process.Type: ApplicationFiled: September 6, 2018Publication date: September 19, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Tsubasa IMAMURA
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Patent number: 10381198Abstract: In one embodiment, a plasma processing apparatus includes: a chamber; an introducing part; a counter electrode; a high-frequency power source; and a plurality of low-frequency power sources. A substrate electrode is disposed in the chamber, a substrate is directly or indirectly placed on the substrate electrode, and the substrate electrode has a plurality of electrode element groups. The introducing part introduces process gas into the chamber. The high-frequency power source outputs a high-frequency voltage for ionizing the process gas to generate plasma. The plurality of low-frequency power sources apply a plurality of low-frequency voltages of 20 MHz or less with mutually different phases for introducing ions from the plasma, to each of the plurality of electrode element groups.Type: GrantFiled: September 25, 2013Date of Patent: August 13, 2019Assignee: Toshiba Memory CorporationInventors: Akio Ui, Hisataka Hayashi, Kazuhiro Tomioka, Hiroshi Yamamoto, Tsubasa Imamura
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Patent number: 10026622Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a hole extending in a first direction in a workpiece. The method includes forming a first film on an upper surface of the workpiece and an upper portion of a side wall of the hole. The method includes forming a second film on the first film. The method includes removing portions of the first and second films from the upper surface of the workpiece so that at least a part of the first and second films formed on the upper portion remain. The method includes removing at least a part of a portion of the workpiece which is exposed through the hole using a second etchant. An etching rate of the first etchant for the first film is higher than an etching rate of the first etchant for the second film.Type: GrantFiled: August 31, 2016Date of Patent: July 17, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Mitsuhiro Omura, Tsubasa Imamura, Itsuko Sakai
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Patent number: 9871054Abstract: According to one embodiment, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The electrode layers have a plurality of terrace portions arranged in a stairstep configuration with a difference in levels. The insulating layer is provided above the terrace portions. The columnar portions extend in a stacking direction of the stacked body through the insulating layer and through the stacked body under the insulating layer. The columnar portions are insulative. The contact portions are provided at side surfaces of the columnar portions on the terrace portions. The contact portions are connected to the terrace portions.Type: GrantFiled: September 6, 2016Date of Patent: January 16, 2018Assignee: Toshiba Memory CorporationInventors: Tsubasa Imamura, Atsushi Takahashi, Toshiyuki Sasaki
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Publication number: 20170301686Abstract: According to one embodiment, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The electrode layers have a plurality of terrace portions arranged in a stairstep configuration with a difference in levels. The insulating layer is provided above the terrace portions. The columnar portions extend in a stacking direction of the stacked body through the insulating layer and through the stacked body under the insulating layer. The columnar portions are insulative. The contact portions are provided at side surfaces of the columnar portions on the terrace portions. The contact portions are connected to the terrace portions.Type: ApplicationFiled: September 6, 2016Publication date: October 19, 2017Inventors: Tsubasa IMAMURA, Atsushi Takahashi, Toshiyuki Sasaki
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Publication number: 20170271170Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a hole extending in a first direction in a workpiece. The method includes forming a first film on an upper surface of the workpiece and an upper portion of a side wall of the hole. The method includes forming a second film on the first film. The method includes removing portions of the first and second films from the upper surface of the workpiece so that at least a part of the first and second films formed on the upper portion remain. The method includes removing at least a part of a portion of the workpiece which is exposed through the hole using a second etchant. An etching rate of the first etchant for the first film is higher than an etching rate of the first etchant for the second film.Type: ApplicationFiled: August 31, 2016Publication date: September 21, 2017Inventors: Mitsuhiro OMURA, Tsubasa IMAMURA, Itsuko SAKAI
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Publication number: 20170263611Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The method further includes simultaneously flowing a first gas with a second gas containing a metal element to form a first opening in the second film and forming a third film containing the metal element on a side surface of the first opening. The method further includes forming a second opening in the first film below the first opening using the second film as a mask.Type: ApplicationFiled: August 31, 2016Publication date: September 14, 2017Inventors: Tsubasa IMAMURA, Atsushi TAKAHASHI, Toshiyuki SASAKI
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Publication number: 20170169996Abstract: In one embodiment, a plasma processing apparatus includes: a chamber; an introducing part; a counter electrode; a high-frequency power source; and a plurality of low-frequency power sources. A substrate electrode is disposed in the chamber, a substrate is directly or indirectly placed on the substrate electrode, and the substrate electrode has a plurality of electrode element groups. The introducing part introduces process gas into the chamber. The high-frequency power source outputs a high-frequency voltage for ionizing the process gas to generate plasma. The plurality of low-frequency power sources apply a plurality of low-frequency voltages of 20 MHz or less with mutually different phases for introducing ions from the plasma, to each of the plurality of electrode element groups.Type: ApplicationFiled: February 24, 2017Publication date: June 15, 2017Inventors: Akio UI, Hisataka HAYASHI, Kazuhiro TOMIOKA, Hiroshi YAMAMOTO, Tsubasa IMAMURA