Abstract: In a data processing system having an instruction buffer, inconsistency between an instruction stored in a main memory and the same instruction present in the instruction buffer occurs at the time of a store operation to the memory if the instruction supplied to the store area of the main memory previously has been prefetched to and is present in the instruction buffer.

Abstract: A data processing system, for executing each instruction, by carrying out a plurality of successive partial processing operations, begins to process the first partial processing operation of an instruction succeeding a defeat overlap instruction before execution of the defeat overlap instruction is finished in response to the detection that a predetermined number of machine cycles is further required for the complete execution of the defeat overlap instruction.

Abstract: A gathering system in an electronic computer including detecting means for detecting the occurrences of each of a plurality of events, a counter group having a plurality of counters each of which counts the number of occurrences of corresponding event until the number thereof becomes 2.sup.l, a storage having a plurality of memory areas, each storing 2.sup.K.multidot.l occurrences of the corresponding event and a processing unit for gathering data representative of the number of occurrences of each of the events from the counter and the storage unit.