Abstract: A semiconductor pseudo memory module includes a multilayer wiring substrate on the surface of which a plurality of DRAMs are provided and on the reverse side of which semiconductor devices of the DRAM controller and multiplexers are provided, these devices being electrically connectetd with one another by a wiring layer. The address signals supplied from outside are converted into column address signals and row address signals by the multiplexer so as to be supplied to each DRAM. Responsive to control signals supplied from outside, the DRAM controller generates a refresh signals for refreshing the DRAMS, which signal is supplied to the DRAM. In this manner, the DRAM may be used as the SRAM.