Patents by Inventor Tsukasa Nakai

Tsukasa Nakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9142771
    Abstract: According to one embodiment, a memory device includes a stacked film stacked in a superlattice structure. The stacked film includes a first layer, a second layer, and a third layer different in composition. The first layer is provided between the second layer and the third layer. The second layer includes a first atom reversibly moved by application of energy. The third layer includes a second atom reversibly moved by application of energy. The second atom is different from the first atom.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: September 22, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Aoi Hidaka, Tsukasa Nakai
  • Patent number: 9136468
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell which stores data with two or more levels. The memory cell includes a structure includes a first electrode layer, a first semiconductor layer, a phase change film, an electrical insulating layer, a second semiconductor layer, and a second electrode layer arranged in order thereof, and the first semiconductor layer and the second semiconductor layer have carrier polarities different from each other.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: September 15, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa Nakai, Masaki Kondo, Hiroyoshi Tanimoto, Nobutoshi Aoki
  • Publication number: 20150255514
    Abstract: An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.
    Type: Application
    Filed: February 25, 2015
    Publication date: September 10, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa NAKAI, Masaki KONDO, Hikari TAJIMA, Hiroki TOKUHIRA, Takashi IZUMIDA, Takashi KURUSU, Nobutoshi AOKI, Takahisa KANEMURA, Tadayoshi UECHI
  • Publication number: 20150255515
    Abstract: An integrated circuit device according to an embodiment, includes a semiconductor member, a first electrode and a second electrode. The semiconductor member includes a first portion of a first conductivity type, a second portion of a second conductivity type, and a third portion of the first conductivity type disposed in this order along a first direction. The first electrode is disposed on a second direction side as viewed from the semiconductor member. The second electrode is disposed on an opposite side of the second direction as viewed from the semiconductor member. An end portion of the second electrode on a first direction side is located in the first direction side rather than that of the first electrode. An end portion of the second electrode on an opposite side of the first direction is located in the first direction side rather than that of the first electrode.
    Type: Application
    Filed: February 25, 2015
    Publication date: September 10, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa NAKAI, Masaki KONDO, Hikari TAJIMA, Hiroki TOKUHIRA, Takashi IZUMIDA, Takashi KURUSU, Nobutoshi AOKI
  • Patent number: 9076685
    Abstract: According to one embodiment, a semiconductor memory device includes a lower gate layer, a stacked body including a plurality of electrode layers and a plurality of insulating layers, alternately stacked on the lower gate layer, a channel body extending within the stacked body from the topmost electrode layer to the lower gate layer, and a memory film provided between the electrode layer and the channel body. The memory film includes a charge storage film. The electrode layer includes a step portion in which a step is formed in a stacking direction of the stacked body. The channel body and the memory film pass through the step portion.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: July 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhito Kuge, Tsukasa Nakai
  • Patent number: 9030881
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer includes a ferroelectric layer.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: May 12, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Tokuhira, Tsukasa Nakai, Hiroyoshi Tanimoto, Masaki Kondo, Toshiyuki Enda, Nobutoshi Aoki
  • Patent number: 9018682
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate, a channel body provided inside a hole piercing the stacked body, and a memory portion provided between the channel body and each of the plurality of electrode layers. The hole has a large diameter portion and a small diameter portion. The diameter of the hole is smaller at the small diameter portion than at the large diameter portion. A thickness of the electrode layer adjacent to the small diameter portion is thicker than a thickness of the electrode layer adjacent to the large diameter portion.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Tsukasa Nakai, Masaki Kondo
  • Patent number: 9019777
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, and a memory cell which is arranged on the semiconductor substrate and comprises a variable resistance element. The variable resistance element comprises a laminated structure including a phase-change element which has at least two different crystalline resistance states by varying a crystalline state, and a magnetoresistive element which has at least two different magnetization resistance states by varying a magnetization state, and applies or does not apply a magnetic field to the phase-change element in accordance with the magnetization state.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Nakai, Jyunichi Ozeki, Nobutoshi Aoki
  • Patent number: 8964459
    Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, a non-magnetic layer formed between the first magnetic layer and the second magnetic layer, a charge storage layer having a first surface and a second surface different from the first surface, the first surface facing the second magnetic layer, a first insulating layer formed between the second magnetic layer and the first surface of the charge storage layer, and a second insulating layer formed on the second surface of the charge storage layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Nakai, Takashi Izumida, Jyunichi Ozeki, Masaki Kondo, Toshiyuki Enda, Nobutoshi Aoki
  • Publication number: 20150008385
    Abstract: According to one embodiment, a memory device includes a stacked film stacked in a superlattice structure. The stacked film includes a first layer, a second layer, and a third layer different in composition. The first layer is provided between the second layer and the third layer. The second layer includes a first atom reversibly moved by application of energy. The third layer includes a second atom reversibly moved by application of energy. The second atom is different from the first atom.
    Type: Application
    Filed: September 3, 2013
    Publication date: January 8, 2015
    Inventors: Aoi HIDAKA, Tsukasa NAKAI
  • Publication number: 20140367758
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate, a channel body provided inside a hole piercing the stacked body, and a memory portion provided between the channel body and each of the plurality of electrode layers. The hole has a large diameter portion and a small diameter portion. The diameter of the hole is smaller at the small diameter portion than at the large diameter portion. A thickness of the electrode layer adjacent to the small diameter portion is thicker than a thickness of the electrode layer adjacent to the large diameter portion.
    Type: Application
    Filed: December 30, 2013
    Publication date: December 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi IZUMIDA, TSUKASA NAKAI, MASAKI KONDO
  • Publication number: 20140346585
    Abstract: According to one embodiment, a semiconductor memory device includes a lower gate layer, a stacked body including a plurality of electrode layers and a plurality of insulating layers, alternately stacked on the lower gate layer, a channel body extending within the stacked body from the topmost electrode layer to the lower gate layer, and a memory film provided between the electrode layer and the channel body. The memory film includes a charge storage film. The electrode layer includes a step portion in which a step is formed in a stacking direction of the stacked body. The channel body and the memory film pass through the step portion.
    Type: Application
    Filed: September 5, 2013
    Publication date: November 27, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobuhito KUGE, Tsukasa NAKAI
  • Publication number: 20140254276
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer includes a ferroelectric layer.
    Type: Application
    Filed: August 8, 2013
    Publication date: September 11, 2014
    Inventors: Hiroki TOKUHIRA, Tsukasa NAKAI, Hiroyoshi TANIMOTO, Masaki KONDO, Toshiyuki ENDA, Nobutoshi AOKI
  • Publication number: 20140241050
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell which stores data with two or more levels. The memory cell includes a structure includes a first electrode layer, a first semiconductor layer, a phase change film, an electrical insulating layer, a second semiconductor layer, and a second electrode layer arranged in order thereof, and the first semiconductor layer and the second semiconductor layer have carrier polarities different from each other.
    Type: Application
    Filed: August 5, 2013
    Publication date: August 28, 2014
    Inventors: Tsukasa NAKAI, Masaki KONDO, Hiroyoshi TANIMOTO, Nobutoshi AOKI
  • Patent number: 8809931
    Abstract: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a substrate, a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate, a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction, an intermediate layer formed on a surface of the second insulating layer, a third insulating layer formed on a surface of the intermediate layer, and a pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Nakai, Nobutoshi Aoki, Takashi Izumida, Masaki Kondo, Toshiyuki Enda
  • Patent number: 8735859
    Abstract: A nonvolatile semiconductor memory device includes: a first interconnect; a second interconnect at a position opposing the first interconnect; and a variable resistance layer between the first interconnect and the second interconnect, the variable resistance layer being capable of reversibly changing between a first state and a second state by a voltage applied via the first interconnect and the second interconnect or a current supplied via the first interconnect and the second interconnect, the first state having a first resistivity, the second state having a second resistivity higher than the first resistivity. Wherein the variable resistance layer has a compound of carbon and silicon as a main component and including hydrogen.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Kuboi, Masayuki Takata, Tsukasa Nakai, Hiroyuki Fukumizu, Yasuhiro Nojiri, Kenichi Ootsuka
  • Publication number: 20140063924
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, and a memory cell which is arranged on the semiconductor substrate and comprises a variable resistance element. The variable resistance element comprises a laminated structure including a phase-change element which has at least two different crystalline resistance states by varying a crystalline state, and a magnetoresistive element which has at least two different magnetization resistance states by varying a magnetization state, and applies or does not apply a magnetic field to the phase-change element in accordance with the magnetization state.
    Type: Application
    Filed: March 6, 2013
    Publication date: March 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa Nakai, Jyunichi Ozeki, Nobutoshi Aoki
  • Patent number: 8581424
    Abstract: According to one embodiment, an information recording/reproducing device including a semiconductor substrate, a first interconnect layer on the semiconductor substrate, a first memory cell array layer on the first interconnect layer, and a second interconnect layer on the first memory cell array layer. The first memory cell array layer comprises an insulating layer having an alignment mark, and a stacked layer structure on the insulating layer and including a storage layer and an electrode layer. All of the layers in the stacked layer structure comprises a material with a permeability of visible light of 1% or more.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Hirai, Tsukasa Nakai, Kohichi Kubo, Chikayoshi Kamata, Takayuki Tsukamoto, Shinya Aoki
  • Publication number: 20130250670
    Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, a non-magnetic layer formed between the first magnetic layer and the second magnetic layer, a charge storage layer having a first surface and a second surface different from the first surface, the first surface facing the second magnetic layer, a first insulating layer formed between the second magnetic layer and the first surface of the charge storage layer, and a second insulating layer formed on the second surface of the charge storage layer.
    Type: Application
    Filed: February 28, 2013
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa NAKAI, Takashi IZUMIDA, Jyunichi OZEKI, Masaki KONDO, Toshiyuki ENDA, Nobutoshi AOKI
  • Publication number: 20130248965
    Abstract: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a substrate, a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate, a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction, an intermediate layer formed on a surface of the second insulating layer, a third insulating layer formed on a surface of the intermediate layer, and a pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction.
    Type: Application
    Filed: March 20, 2013
    Publication date: September 26, 2013
    Inventors: Tsukasa NAKAI, Nobutoshi AOKI, Takashi IZUMIDA, Masaki KONDO, Toshiyuki ENDA