Patents by Inventor Tsukasa Ohoka
Tsukasa Ohoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7576524Abstract: In a constant voltage generating apparatus where an output circuit is controlled in accordance with a control voltage, a voltage detection signal generating circuit generates a voltage detection signal in accordance with a difference between an output voltage signal of the output circuit and a first reference signal. A current detection signal generating circuit generates a current detection signal in accordance with a difference between an output current signal of the output circuit and a second reference signal. A control current generating circuit generates a control current in accordance with the voltage detection signal and the current detection signal. A control current-to-control voltage converting circuit converts the control current into the control voltage.Type: GrantFiled: November 2, 2006Date of Patent: August 18, 2009Assignee: NEC Electronics CorporatioonInventor: Tsukasa Ohoka
-
Publication number: 20070108949Abstract: In a constant voltage generating apparatus where an output circuit is controlled in accordance with a control voltage, a voltage detection signal generating circuit generates a voltage detection signal in accordance with a difference between an output voltage signal of the output circuit and a first reference signal. A current detection signal generating circuit generates a current detection signal in accordance with a difference between an output current signal of the output circuit and a second reference signal. A control current generating circuit generates a control current in accordance with the voltage detection signal and the current detection signal. A control current-to-control voltage converting circuit converts the control current into the control voltage.Type: ApplicationFiled: November 2, 2006Publication date: May 17, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Tsukasa Ohoka
-
Patent number: 6576481Abstract: When films of Ru(C2H5C5H4)2 are formed on a substrate by means of a thermal CVD method, the films are also deposited on members around the substrate, resulting in the formation of particles on the substrate and hence a reduction in the manufacturing yield. Thus, it is necessary to clean the interior of the reaction chamber, but in a conventional cleaning process, a cleaning time is long and hence manufacturing efficiency is low, increasing manufacturing costs. To improve these, a method of manufacturing semiconductor devices according to the present invention includes: a deposition process for forming a film containing Ru on a substrate in a reaction chamber; and a cleaning process for supplying a ClF3 gas to the reaction chamber so as to remove films, which were deposited on an inner surface of the reaction chamber in the deposition process, through thermochemical reactions.Type: GrantFiled: September 26, 2001Date of Patent: June 10, 2003Assignee: Hitachi Kokusai Electric Inc.Inventors: Hideharu Itatani, Masayuki Tsuneda, Atsushi Sano, Tsukasa Ohoka
-
Patent number: 6538291Abstract: An input protection circuit comprising a MOS transistor which has a P− type semiconductor layer provided with an N+ type drain region of rectangular shape and a P+ type backgate contact region surrounding the same, the P+ type backgate contact region having the shape of a frame parallel to each side of the drain region. In the input protection circuit, negative-level static electricity applied to an electrode pad is discharged by means of a forward bias to the PN junction between the semiconductor layer and the drain region. Here, N− type diffusion layers of U shape are formed between the drain region and the backgate contact region in the semiconductor layer at a predetermined distance from the drain region, so as to surround the vicinities of both longitudinal ends of the drain region. Thereby, the current path through the forward-biased PN junction is partially increased in resistance to avoid local current concentration for improved breakdown voltage.Type: GrantFiled: September 27, 2000Date of Patent: March 25, 2003Assignee: NEC CorporationInventor: Tsukasa Ohoka
-
Publication number: 20030037802Abstract: A ruthenium film, an osmium film, and an oxide thereof, deposited or adhered on the inside of a semiconductor treating apparatus are effectively removed. To accomplish this, an oxygen-atom donating gas and a halogen gas are supplied to the apparatus, whereby a reaction product deposited or adhered on the inside of the apparatus can be rapidly and effectively removed. In addition, to providing a stable operation, the formation of a thin film with high qualities and the production of a semiconductor device with a high yield are also realized.Type: ApplicationFiled: July 23, 2002Publication date: February 27, 2003Applicant: Hitachi, Ltd.Inventors: Miwako Nakahara, Toshiyuki Arai, Satoshi Yamamoto, Tsukasa Ohoka, Atsushi Sano, Hideharu Itaya, Harunobu Sakuma
-
Patent number: 6461961Abstract: A semiconductor device manufacturing method is obtained which is capable of depositing a ruthenium film with excellent homogeneity in the film quality and excellent reproducibility of the surface morphology. The semiconductor device manufacturing method of the present invention includes heating a silicon wafer up to a temperature of 290-350° C.Type: GrantFiled: September 27, 2001Date of Patent: October 8, 2002Assignee: Hitachi Kokusai Electric Inc.Inventors: Atsushi Sano, Tsukasa Ohoka
-
Publication number: 20020072211Abstract: When films of Ru(C2H5C5H4)2 are formed on a substrate by means of a thermal CVD method, the films are also deposited on members around the substrate, resulting in the formation of particles on the substrate and hence a reduction in the manufacturing yield. Thus, it is necessary to clean the interior of the reaction chamber, but in a conventional cleaning process, a cleaning time is long and hence manufacturing efficiency is low, increasing manufacturing costs. To improve these, a method of manufacturing semiconductor devices according to the present invention includes: a deposition process for forming a film containing Ru on a substrate in a reaction chamber; and a cleaning process for supplying a CIF3 gas to the reaction chamber so as to remove films, which were deposited on an inner surface of the reaction chamber in the deposition process, through thermochemical reactions.Type: ApplicationFiled: September 26, 2001Publication date: June 13, 2002Inventors: Hideharu Itatani, Masayuki Tsuneda, Atsushi Sano, Tsukasa Ohoka
-
Publication number: 20020055254Abstract: A semiconductor device manufacturing method is obtained which is capable of depositing a ruthenium film with excellent homogeneity in the film quality and excellent reproducibility of the surface morphology. The semiconductor device manufacturing method of the present invention includes heating a silicon wafer up to a temperature of 290-350° C.Type: ApplicationFiled: September 27, 2001Publication date: May 9, 2002Inventors: Atsushi Sano, Tsukasa Ohoka
-
Patent number: 6303954Abstract: A semiconductor device comprises a semiconductor layer on an insulator film that is contiguous to a semiconductor substrate. A component, such as a high-voltage diode, forming region is provided in the semiconductor layer and electrically insulated from other component forming regions. A substrate access region is provided in the semiconductor layer and electrically insulated from the component forming region. The substrate access region includes a conductive zone, which extends from the surface down through the semiconductor layer and insulator film to the substrate. A substrate contact is in contact with the conductive zone. The substrate contact and an anode contact of the diode are subject to the same potential.Type: GrantFiled: June 11, 1999Date of Patent: October 16, 2001Assignee: NEC CorporationInventor: Tsukasa Ohoka
-
Patent number: 5593915Abstract: A method of manufacturing a semiconductor device includes the following steps. A silicon oxide film having a predetermined film thickness is formed on a smooth major surface of a first silicon substrate of a first conductivity type having a first region wherein a power transistor is to be formed. The major surface of the first silicon substrate is bonded to a smooth major surface of a second silicon substrate having one of the first conductivity type and a second conductivity type. The other surface of the second silicon substrate bonded to the first silicon substrate is polished to form a silicon layer having a predetermined film thickness and a second region wherein a transistor constituting a control circuit for driving the power transistor is to be formed. The silicon layer and the silicon oxide film are removed from a predetermined portion in the first region.Type: GrantFiled: September 6, 1994Date of Patent: January 14, 1997Assignee: NEC CorporationInventor: Tsukasa Ohoka
-
Patent number: 5534726Abstract: A semiconductor device where an aluminum electrode surrounds an output electrode of an element, is provide by a detector electrode formed on a ring shaped space between the output electrode and the aluminum electrode. Sliding of the aluminum electrode toward the output electrode which occurs in an aging degradation, is detected by contact between the aluminum electrode and the detector electrode.Type: GrantFiled: August 25, 1994Date of Patent: July 9, 1996Assignee: NEC CorporationInventor: Tsukasa Ohoka
-
Patent number: 5420064Abstract: According to this invention, there is provided a method of manufacturing a semiconductor device, including the steps of anisotropically etching a surface of an n-type monocrystalline silicon substrate having the (100) plane to form a V-shaped isolation groove having a depth d.sub.1, performing ion implantation and performing annealing and diffusion to a surface of the V-shaped isolation groove to form an n.sup.+ -type buried layer, depositing a silicon dioxide film having a thickness d.sub.2 on a surface of the n.sup.+ -type buried layer, forming a polycrystalline silicon film on a surface of the silicon dioxide film, abrading and polishing the polycrystalline silicon film to have a thickness d.sub.3, adhering a monocrystalline silicon support substrate having a thickness d.sub.Type: GrantFiled: September 22, 1994Date of Patent: May 30, 1995Assignee: NEC CorporationInventors: Kensuke Okonogi, Tsukasa Ohoka
-
Patent number: 5356827Abstract: A method of manufacturing a semiconductor device includes the following steps. A wide groove portion is formed in a predetermined portion of one major surface of a first semiconductor substrate. A first insulating film is formed on the bottom surface of the groove portion. The major surface of the first semiconductor substrate except for the first insulating film is polished to form a mirror-polished surface on the same level as the surface of the first insulating film. One major surface of a second semiconductor substrate is bonded to the mirror-polished surface of the first semiconductor substrate and the surface of the first insulating film by direct bonding, and the resultant structure is heat-treated, thereby forming a composite semiconductor substrate. A groove having a ring-like planar shape is formed to extend from the other major surface of the first semiconductor substrate constituting the composite semiconductor substrate to the first insulating film.Type: GrantFiled: March 12, 1993Date of Patent: October 18, 1994Assignee: NEC CorporationInventor: Tsukasa Ohoka