Patents by Inventor Tsunehiro Tobita
Tsunehiro Tobita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6275436Abstract: A control method and system when a flash memory is used. as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data.Type: GrantFiled: May 23, 2000Date of Patent: August 14, 2001Assignees: Hitachi, LTD, Hitachi Keiyo Engineering Co., Ltd., Hitachi ULSI Engineering Corp.Inventors: Tsunehiro Tobita, Jun Kitahara, Takashi Tsunehiro, Kunihiro Katayama, Ryuichi Hattori, Yukihiro Seki, Hajime Yamagami, Takashi Totsuka, Takeshi Wada, Yosio Takaya, Manabu Saito, Kenichi Kaki, Takao Okubo, Takashi Kikuchi, Masamichi Kishi, Takeshi Suzuki, Shigeru Kadowaki
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Patent number: 6272610Abstract: A semiconductor file memory device, and an information processing system incorporating the device, uses flash memories to achieve fast file access performance.Type: GrantFiled: March 9, 1994Date of Patent: August 7, 2001Assignee: Hitachi, Ltd.Inventors: Kunihiro Katayama, Kenichi Kaki, Jun Kitahara, Tsunehiro Tobita, Kazunori Furusawa
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Publication number: 20010008021Abstract: A computer management system attains, through one line, the uniform and steady system management through an agent such as monitoring of fault and power control in a computer connected by LAN as well as a public line, and system management for an off-state of the computer or abnormal operation state of the computer such as remote power control and notice and diagnosis of critical fault by the direct connection with a service processor through the line.Type: ApplicationFiled: January 30, 2001Publication date: July 12, 2001Inventors: Ichiro Ote, Hiroshi Furukawa, Hiroaki Washimi, Yuichi Kobayashi, Shigeru Sakurai, Teiji Karasaki, Yuji Miyagawa, Masami Murai, Tsunehiro Tobita
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Publication number: 20010007119Abstract: A semiconductor file memory device, and an information processing system incorporating the device, uses flash memories to achieve fast file access performance.Type: ApplicationFiled: February 28, 2001Publication date: July 5, 2001Inventors: Kunihiro Katayama, Kenichi Kaki, Jun Kitahara, Tsunehiro Tobita, Kazunori Furusawa
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Patent number: 6199180Abstract: A computer management system includes an agent connected to a computer to be managed for executing instructions on the computer to be managed, a service processor board having a processor independent from the computer to be managed for monitoring fault in the computer to be managed and controlling power of the computer to be managed, a manager for executing instructions on a management computer and conducting controls such as fault monitoring and power control through the agent over a network including a public line, and a service processor manager directly connected to the service processor for conducting remote power-on and receiving and diagnosing critical fault. The service processor and the service processor manager are provided with switching circuits for switching an asynchronous interface for remotely connecting to the computer to be managed and an asynchronous interface for directly connecting to a local processor of the service processor.Type: GrantFiled: December 30, 1999Date of Patent: March 6, 2001Assignee: Hitachi, Ltd.Inventors: Ichiro Ote, Hiroshi Furukawa, Hiroaki Washimi, Yuichi Kobayashi, Shigeru Sakurai, Teiji Karasaki, Yuji Miyagawa, Masami Murai, Tsunehiro Tobita
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Patent number: 6108731Abstract: A plurality of processor elements (31 to 34) are disposed on a main board (710) in line in parallel with a first edge of the main substrate (710). Expansion board slots (331 to 336) into which an expansion board for mounting an I/O interface thereon is plugged and a memory connector (341) to which a memory board for mounting a memory thereon is connected are disposed in a region of the main substrate opposite to the first edge. The long sides of the expansion board slots (331 to 336) and the memory board connector (341) are in parallel with the first edge. A bridge LSI for executing protocol conversion between processor buses (210, 211, 212) and an I/O bus (230) and memory controllers (151, 152) for controlling memory access are disposed in regions adjacent to both the expansion board slots and the processor elements.Type: GrantFiled: August 4, 1998Date of Patent: August 22, 2000Assignee: Hitachi, Ltd.Inventors: Shinichi Suzuki, Tsunehiro Tobita, Yoshitsugu Ichieda, Hiroyuki Hodo, Mihoko Kudou, Tetsuo Hiramitsu, Hideki Osaka, Tsutomu Hara
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Patent number: 6094674Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.Type: GrantFiled: June 29, 1998Date of Patent: July 25, 2000Assignee: Hitachi, Ltd.Inventors: Ryuichi Hattori, Toshihiko Ogura, Takashi Oeda, Koichi Okazawa, Hideki Osaka, Tsunehiro Tobita, Tsutomu Hara
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Patent number: 6078520Abstract: A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data.Type: GrantFiled: July 21, 1999Date of Patent: June 20, 2000Assignees: Hitachi, Ltd., Hitachi Keiyo Engineering Co., Ltd., Hitachi ULSIInventors: Tsunehiro Tobita, Jun Kitahara, Takashi Tsunehiro, Kunihiro Katayama, Ryuichi Hattori, Yukihiro Seki, Hajime Yamagami, Takashi Totsuka, Takeshi Wada, Yosio Takaya, Manabu Saito, Kenichi Kaki, Takao Okubo, Takashi Kikuchi, Masamichi Kishi, Takeshi Suzuki, Shigeru Kadowaki
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Patent number: 6061238Abstract: An information processing apparatus includes a plurality of processor boards arranged parallelly on the main board and the DC--DC converters for generating operation voltages for processor devices each disposed between the adjacent processor boards. Further, a metal plate with high thermal conductivity is placed in close contact with an area of each of the processor boards where devices generating a large amount of heat are mounted. Heat dissipating fins are joined to the surface of each of the metal plates so that when the processor boards are mounted on the main board, the heat dissipating fins do not contact the DC--DC converter. The heat dissipating fins and the DC--DC converters are arranged so that they are vertically disposed one over the other with respect to the main board.Type: GrantFiled: June 28, 1999Date of Patent: May 9, 2000Assignee: Hitachi, Ltd.Inventors: Hideyuki Osakada, Yukihiro Seki, Tsunehiro Tobita, Junichi Taguri, Hiroshi Mochizuki
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Patent number: 6044476Abstract: A computer management system includes an agent connected to a computer to be managed for executing instructions on the computer to be managed, a service processor board having a processor independent from the computer to be managed for monitoring fault in the computer to be managed and controlling power of the computer to be managed, a manager for executing instructions on a management computer and conducting controls such as fault monitoring and power control through the agent over a network including a public line, and a service processor manager directly connected to the service processor for conducting remote power-on and receiving and diagnosing critical fault. The service processor and the service processor manager are provided with switching circuits for switching an asynchronous interface for remotely connecting to the computer to be managed and an asynchronous interface for directly connecting to a local processor of the service processor.Type: GrantFiled: August 31, 1998Date of Patent: March 28, 2000Assignee: Hitachi, Ltd.Inventors: Ichiro Ote, Hiroshi Furukawa, Hiroaki Washimi, Yuichi Kobayashi, Shigeru Sakurai, Teiji Karasaki, Yuji Miyagawa, Masami Murai, Tsunehiro Tobita
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Patent number: 5973964Abstract: A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data.Type: GrantFiled: October 30, 1998Date of Patent: October 26, 1999Assignees: Hitachi, Ltd., Hitachi Keiyo Engineering Co., Ltd., Hitachi ULSI Engineering Co., Ltd.Inventors: Tsunehiro Tobita, Jun Kitahara, Takashi Tsunehiro, Kunihiro Katayama, Ryuichi Hattori, Yukihiro Seki, Hajime Yamagami, Takashi Totsuka, Takeshi Wada, Yosio Takaya, Manabu Saito, Kenichi Kaki, Takao Okubo, Takashi Kikuchi, Masamichi Kishi, Takeshi Suzuki, Shigeru Kadowaki
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Patent number: 5862083Abstract: A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data.Type: GrantFiled: April 30, 1996Date of Patent: January 19, 1999Assignees: Hitachi, Ltd., Hitachi Keiyo Engineering Co., Ltd., Hitachi ULSI Engineering Corp.Inventors: Tsunehiro Tobita, Jun Kitahara, Takashi Tsunehiro, Kunihiro Katayama, Ryuichi Hattori, Yukihiro Seki, Hajime Yamagami, Takashi Totsuka, Takeshi Wada, Yosio Takaya, Manabu Saito, Kenichi Kaki, Takao Okubo, Takashi Kikuchi, Masamichi Kishi, Takeshi Suzuki, Shigeru Kadowaki
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Patent number: 5815652Abstract: A computer management system includes an agent connected to a computer to be managed for executing instructions on the computer to be managed, a service processor board having a processor independent from the computer to be managed for monitoring fault in the computer to be managed and controlling power of the computer to be managed, a manager for executing instructions on a management computer and conducting controls such as fault monitoring and power control through the agent over a network including a public line, and a service processor manager directly connected to the service processor for conducting remote power-on and receiving and diagnosing critical fault. The service processor and the service processor manager are provided with switching circuits for switching an asynchronous interface for remotely connecting to the computer to be managed and an asynchronous interface for directly connecting to a local processor of the service processor.Type: GrantFiled: May 30, 1996Date of Patent: September 29, 1998Assignee: Hitachi, Ltd.Inventors: Ichiro Ote, Hiroshi Furukawa, Hiroaki Washimi, Yuichi Kobayashi, Shigeru Sakurai, Teiji Karasaki, Yuji Miyagawa, Masami Murai, Tsunehiro Tobita
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Patent number: 5781434Abstract: An information processing system includes a modem communicating with a remote console through a telephone line, an information processing apparatus communicating with the remote console through the modem, a service processor, a power supply continuously supplying power to the modem and the service processor, a power supply supplying power to the information processing apparatus according to commands from the service processor, and a switch connecting the modem to the service processor or the information processing apparatus in accordance with a switching signal from the service processor. The service processor controls the switch to connect the modem to the service processor when the information processing apparatus power supply is in the off state.Type: GrantFiled: October 13, 1995Date of Patent: July 14, 1998Assignees: Hitachi, Ltd., Hitachi Chubu Software, Ltd.Inventors: Tsunehiro Tobita, Yukihiro Seki, Ryuichi Hattori, Yuji Miyagawa, Shigeru Sakurai, Michiyuki Suzuki, Ichiro Ote
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Patent number: 5774656Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.Type: GrantFiled: May 3, 1995Date of Patent: June 30, 1998Assignee: Hitachi, Ltd.Inventors: Ryuichi Hattori, Toshihiko Ogura, Takashi Oeda, Koichi Okazawa, Hideki Osaka, Tsunehiro Tobita, Tsutomu Hara
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Patent number: 5724591Abstract: A multiprocessor system is provided with processor units which are grouped beforehand into some groups, a system status monitoring unit for monitoring a key input operation of a keyboard, a power demand monitoring unit for calculating the difference between the total power demand of the processor units at the present time and the total power demand of the processor units in a low power-demand mode which is measured beforehand, when the key input operation is not carried out in a normal operation mode for a predetermined time, and an operation clock controller for successively reducing or stopping operation clocks supplied to the respective processor units for each group in turn to shift the current mode to the low power-demand mode. With this construction, a power variation which occurs at the time of the switching operation between the normal operation mode and the low power-demand mode or at the time of power supply/power shut-off can be reduced.Type: GrantFiled: January 26, 1996Date of Patent: March 3, 1998Assignee: Hitachi, Ltd.Inventors: Tsutomu Hara, Takashi Maruyama, Hitoshi Yoshidome, Ryuichi Hattori, Tsunehiro Tobita
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Patent number: 5530673Abstract: A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data.Type: GrantFiled: April 8, 1994Date of Patent: June 25, 1996Assignees: Hitachi, Ltd., Hitachi Keiyo Engineering Co., Ltd., Hitachi ULSI Engineering Corp.Inventors: Tsunehiro Tobita, Jun Kitahara, Takashi Tsunehiro, Kunihiro Katayama, Ryuichi Hattori, Yukihiro Seki, Hajime Yamagami, Takashi Totsuka, Takeshi Wada, Yosio Takaya, Manabu Saito, Kenichi Kaki, Takao Okubo, Takashi Kikuchi, Masamichi Kishi, Takeshi Suzuki, Shigeru Kadowaki