Patents by Inventor Tsung-Che TSAI
Tsung-Che TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210104512Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bi-directional silicon controlled rectifiers (SCRs) and methods of manufacture. The structure includes: a plurality of diffusion regions; a plurality of p-type (P+) wells adjacent to the diffusion regions, wherein the P+ wells are directly connected; and a plurality of n-type (N+) wells adjacent to the P+ wells.Type: ApplicationFiled: October 3, 2019Publication date: April 8, 2021Inventors: Souvick MITRA, Alain F. LOISEAU, Robert J. GAUTHIER, JR., You LI, Tsung-Che TSAI
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Publication number: 20200411504Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.Type: ApplicationFiled: June 27, 2019Publication date: December 31, 2020Inventors: Souvick MITRA, Robert J. GAUTHIER, JR., Alain F. LOISEAU, You LI, Tsung-Che TSAI
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Patent number: 10692852Abstract: Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.Type: GrantFiled: October 26, 2018Date of Patent: June 23, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Alain Loiseau, You Li, Mickey Yu, Tsung-Che Tsai, Souvick Mitra, Robert J. Gauthier, Jr.
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Publication number: 20200135715Abstract: Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: Alain Loiseau, You Li, Mickey Yu, Tsung-Che Tsai, Souvick Mitra, Robert J. Gauthier, JR.
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Patent number: 10541236Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge structures with reduced capacitance and methods of manufacture. The structure includes: a plurality of fin structures provided in at least one N+ type region and at least one P+ region; and a plurality of gate structures disposed over the plurality of fin structures and within the at least one N+ type region and one P+ region, the plurality of gate structures being separated in a lengthwise direction between the at least one N+ type region and the least one P+ region.Type: GrantFiled: June 26, 2018Date of Patent: January 21, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Souvick Mitra, Mickey Yu, Alain F. Loiseau, You Li, Robert J. Gauthier, Jr., Tsung-Che Tsai
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Publication number: 20200021109Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to electrostatic discharge clamp structures and methods of manufacture. The structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.Type: ApplicationFiled: July 12, 2018Publication date: January 16, 2020Inventors: You LI, Alain F. LOISEAU, Souvick MITRA, Tsung-Che TSAI, Mickey YU, Robert J. GAUTHIER, JR.
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Publication number: 20190393209Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge structures with reduced capacitance and methods of manufacture. The structure includes: a plurality of fin structures provided in at least one N+ type region and at least one P+ region; and a plurality of gate structures disposed over the plurality of fin structures and within the at least one N+ type region and one P+ region, the plurality of gate structures being separated in a lengthwise direction between the at least one N+ type region and the least one P+ region.Type: ApplicationFiled: June 26, 2018Publication date: December 26, 2019Inventors: Souvick MITRA, Mickey YU, Alain F. LOISEAU, You LI, Robert J. GAUTHIER, JR., Tsung-Che TSAI
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Patent number: 10381826Abstract: Integrated circuits with electrostatic discharge (ESD) protection and methods of providing ESD protection in an integrated circuit are provided. An ESD protection circuit the ESD protection circuit may incorporate a transistor, such as a MOSFET, and a voltage limiter coupled to a gate of the transistor. The voltage limiter may be configured such that with an ESD disturbance on the voltage supply rail, Vdd, a gate voltage of the transistor of the ESD protection circuit is held below the supply voltage (Vdd) inducing base current, Isub, within the transistor to effectively shunt a current arising from the ESD event from the voltage supply rail Vdd to the voltage supply rail Vss.Type: GrantFiled: April 22, 2016Date of Patent: August 13, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wei Gao, Manjunatha Prabhu, Tsung-Che Tsai
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Publication number: 20190229207Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).Type: ApplicationFiled: January 24, 2018Publication date: July 25, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Tsung-Che Tsai, Alain F. Loiseau, Robert J. Gauthier, JR., Souvick Mitra, You Li, Mickey H. Yu
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Patent number: 10361293Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).Type: GrantFiled: January 24, 2018Date of Patent: July 23, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Tsung-Che Tsai, Alain F. Loiseau, Robert J. Gauthier, Jr., Souvick Mitra, You Li, Mickey H. Yu
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Patent number: 10340266Abstract: Methods of forming a high voltage ESD GGNMOS using embedded gradual PN junction in the source region and the resulting devices are provided. Embodiments include a device having a substrate including a device region with an ESD protection circuit; a gate over the device region; a source region in the device region having a N+ implant and a P+ implant laterally separated on a first side of the gate; and a drain region in the device region on a second side of the gate, opposite the first.Type: GrantFiled: October 2, 2017Date of Patent: July 2, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Yohann Frederic Michel Solaro, Chai Ean Gill, Tsung-Che Tsai
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Patent number: 10290626Abstract: Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a portion of a p-sub; forming a HVPDDD region in a portion of the DNW region; forming a first and a second NW in a portion of the DNW region, the second NW between the first NW and the HVPDDD region and laterally separated from the HVPDDD region; forming a PW in a portion of the HVPDDD region; forming an N+ implant in a portion of the first NW and a P+ implant in a portion of the PW; forming a first, a second and a third fin structures over the first and the second NW and the PW, respectively; and forming a N+ S/D, a P+ S/D and a P+ S/D over the first, the second and the third fin structures, respectively.Type: GrantFiled: January 12, 2018Date of Patent: May 14, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: You Li, Alain Loiseau, Tsung-Che Tsai, Mickey Yu, Souvick Mitra, Robert Gauthier, Jr.
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Publication number: 20190103398Abstract: Methods of forming a high voltage ESD GGNMOS using embedded gradual PN junction in the source region and the resulting devices are provided. Embodiments include a device having a substrate including a device region with an ESD protection circuit; a gate over the device region; a source region in the device region having a N+ implant and a P+ implant laterally separated on a first side of the gate; and a drain region in the device region on a second side of the gate, opposite the first.Type: ApplicationFiled: October 2, 2017Publication date: April 4, 2019Inventors: Yohann Frederic Michel SOLARO, Chai Ean GILL, Tsung-Che TSAI
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Patent number: 10170459Abstract: Methods to forming low trigger-voltage ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including a first-type well area in an ESD region; forming a base junction of the first-type along the perimeter of the ESD region; forming a shallow trench isolation (STI) region adjacent the base junction; forming alternate emitter and collector junctions of a second-type adjacent the STI region, parallel to and spaced from each other by parallel additional STI regions; forming at least one gate perpendicular to and over a collector junction; and forming a floating ESD nodes of the first-type in the collector junction adjacent one side of the at least one gate.Type: GrantFiled: June 12, 2017Date of Patent: January 1, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Tsung-Che Tsai, Manjunatha Govinda Prabhu, Vaddagere Nagaraju Vasantha Kumar
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Publication number: 20180358350Abstract: Methods to forming low trigger-voltage ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including a first-type well area in an ESD region; forming a base junction of the first-type along the perimeter of the ESD region; forming a shallow trench isolation (STI) region adjacent the base junction; forming alternate emitter and collector junctions of a second-type adjacent the STI region, parallel to and spaced from each other by parallel additional STI regions; forming at least one gate perpendicular to and over a collector junction; and forming a floating ESD nodes of the first-type in the collector junction adjacent one side of the at least one gate.Type: ApplicationFiled: June 12, 2017Publication date: December 13, 2018Inventors: Tsung-Che TSAI, Manjunatha Govinda PRABHU, Vaddagere Nagaraju VASANTHA KUMAR
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Patent number: 10134726Abstract: A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.Type: GrantFiled: October 24, 2016Date of Patent: November 20, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Che Tsai, Jam-Wem Lee
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Patent number: 10096587Abstract: Diode structures and methods of fabricating diode structures. First and second gate structures are formed with the second gate structure arranged parallel to the first gate structure. First and second fins are formed that extend vertically from a top surface of a substrate. The first and second fins are arranged between the first gate structure and the second gate structure. A contact structure is coupled with the first fin and the second fin. The contact structure is laterally arranged between the first gate structure and the second gate structure.Type: GrantFiled: October 26, 2017Date of Patent: October 9, 2018Assignee: GLOBAL FOUNDRIES Inc.Inventors: Mickey Yu, Alain Loiseau, Souvick Mitra, Tsung-Che Tsai, You Li, Robert J. Gauthier, Jr.
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Patent number: 10037988Abstract: A method of forming a HV lateral PNP BJT with a pulled back isolation structure and a polysilicon gate covering a part of the NW+HVNDDD base region and a part of the collector extension (HVPDDD) and the resulting device are provided. Embodiments include forming a DVNWELL in a portion of a p-sub; forming a HVPDDD in a portion of the DVNWELL; forming a LVPW in a portion of the HVPDDD; forming a first and a second NW laterally separated in a portion of the DVNWELL, the first and second NW being laterally separated from the HVPDDD; forming a N+ base, a P+ emitter, and a P+ collector in an upper portion of the first and second NW and LVPW, respectively; forming a STI structure between the P+ emitter and P+ collector in a portion of the DVNWELL, HVPDDD, and LVPW, respectively; and forming a SAB layer over the STI structure.Type: GrantFiled: August 24, 2017Date of Patent: July 31, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Yohann Frederic Michel Solaro, Rudy Octavius Sihombing, Tsung-Che Tsai, Chai Ean Gill
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Patent number: 10032761Abstract: Electronic devices and methods of producing such electronic devices are provided. In an exemplary embodiment, a method of producing an electronic device includes forming a protected circuit and an ESD circuit, where the ESD circuit is configured to discharge an electrostatic discharge (ESD) to a ground such that the ESD bypasses the protected circuit. An ESD transistor is formed in the ESD circuit, where the ESD transistor includes a source and a drain. The ESD transistor also includes a gate with a gate width perpendicular to a gate length, where the gate length is measured across the gate from the source to the drain. A trigger voltage of the ESD transistor is set by adjusting the gate width.Type: GrantFiled: April 7, 2017Date of Patent: July 24, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Vvss Satyasuresh Choppalli, Vaddagere Nagaraju Vasantha Kumar, Tsung-Che Tsai
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Patent number: 10032765Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a deep well with a drain well overlying the deep well. A first source well also overlies the deep well, where the first source well includes a first source well concentration of conductivity determining impurities. A second source well overlies the first source well, where the second source well includes a second concentration of conductivity determining impurities that is higher than the first source well concentration. A drain overlies the drain well and a source overlies the second source well. A channel is defined between the source and the drain and a gate overlies the channel.Type: GrantFiled: May 18, 2017Date of Patent: July 24, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Yohann Frederic Michel Solaro, Vvss Satyasuresh Choppalli, Tsung-Che Tsai, Chai Ean Gill, Ruchil Kumar Jain