Abstract: A method for forming a semiconductor structure is provided. The method includes forming a spacer layer along a first fin structure and a second fin structure, etching a first portion of the spacer layer and the first fin structure to form first fin spacers and a first recess between the first fin spacers, etching a second portion of the spacer layer and the second fin structure to form second fin spacers and a second recess between the second fin spacers, and forming a first source/drain feature in the first recess and a second source/drain feature in the second recess. The second fin structure is wider than the first fin structure. The first fin spacers have a first height, and the second fin spacers have a second height that is greater than the first height.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: The present disclosure provides a battery charging system and method. The battery charging method includes: determining a degree of healthy of a battery module according to an evaluation mechanism; setting a charging standard according to the degree of healthy; by handshaking with a charger, setting a charging voltage for the charger according to the charging standard to charge the battery module; and by the charger, perform a charging operation on the battery module until a fully charged condition is satisfied.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.

Abstract: In an embodiment, a circuit includes: an error amplifier; a temperature sensor, wherein the temperature sensor is coupled to the error amplifier; a discrete time controller coupled to the error amplifier, wherein the discrete time controller comprises digital circuitry; a multiple bits quantizer coupled to the discrete time controller, wherein the multiple bits quantizer produces a digital code output; and a heating array coupled to the multiple bits quantizer, wherein the heating array is configured to generate heat based on the digital code output.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first patterned layer over a substrate; forming a second patterned layer over the substrate and alternately arranged with the first patterned layer; performing an etching, thereby forming an arched surface of the first patterned layer and an arched surface of the second patterned layer; forming a sacrificial layer over the first patterned layer and the second patterned layer, wherein a plurality of air gaps are defined by the substrate, the first patterned layer, the second patterned layer and the sacrificial layer; removing the sacrificial layer above the plurality of air gaps, thereby forming a planar top surface of the first patterned layer and a planar top surface of the second patterned layer; and patterning the substrate using the first patterned layer and the second patterned layer as a mask.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure. The method includes: forming a conformal layer over a first patterned layer over a substrate; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to form a second patterned layer and a patterned conformal layer; performing a second etching to remove a portion of the first patterned layer to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to remove a portion of the second patterned layer to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure. The method includes: forming a conformal layer over a first patterned layer over a substrate; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to form a second patterned layer and a patterned conformal layer; performing a second etching to remove a portion of the first patterned layer to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to remove a portion of the second patterned layer to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first patterned layer over a substrate; forming a second patterned layer over the substrate and alternately arranged with the first patterned layer; performing an etching, thereby forming an arched surface of the first patterned layer and an arched surface of the second patterned layer; forming a sacrificial layer over the first patterned layer and the second patterned layer, wherein a plurality of air gaps are defined by the substrate, the first patterned layer, the second patterned layer and the sacrificial layer; removing the sacrificial layer above the plurality of air gaps, thereby forming a planar top surface of the first patterned layer and a planar top surface of the second patterned layer; and patterning the substrate using the first patterned layer and the second patterned layer as a mask.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. A first patterned layer and a second patterned layer are formed over a substrate. The second patterned layer and the first patterned layer are alternately arranged. An etching is performed, thereby forming an arched surface of the first patterned layer and an arched surface of the second patterned layer. A sacrificial layer is formed over the first patterned layer and the second patterned layer, wherein a plurality of air gaps are defined by the substrate, the first patterned layer, the second patterned layer and the sacrificial layer. The sacrificial layer above the plurality of air gaps is removed, and a planar top surface of the first patterned layer and a planar top surface of the second patterned are thereby formed. The substrate is then patterned using the first patterned layer and the second patterned layer as a mask.

Abstract: A method of manufacturing a semiconductor structure includes the following operations. A buffer layer is formed over a substrate. A first top hard mask is formed on the buffer layer, in which the first top hard mask has a first trench to expose a first portion of the buffer layer. A spacer layer is formed to cover a sidewall of the first trench and an upper surface of the first top hard mask and the first portion of the buffer layer to form a second trench over the first portion. The top portion and the bottom portion are etched to form a thinned top portion and a thinned bottom portion. A second top hard mask is formed in the second trench. The thinned top portion and the vertical portion of the spacer layer are removed.

Abstract: An automatic nucleic acid detection system and a method thereof are disclosed. The automatic nucleic acid detection method includes: performing, by an automatic control subsystem, on a nucleic acid extraction machine platform, a nucleic acid extraction on one or more specimens in a sample tray to generate one or more corresponding nucleic acids in the sample tray; distributing, by the automatic control subsystem, on a nucleic acid distribution machine platform, the nucleic acid in each hole of the sample tray and a first reagent into a plurality of holes of a detection tray, wherein the number of holes of the detection tray is greater than that of the sample tray; and performing, by the automatic control subsystem, on a nucleic acid detection machine platform, a nucleic acid detection on the detection tray.

Abstract: A gas sensing device comprises a silicon substrate, an insulating layer, a plasma treatment layer, a metal electrode and a sensing layer. The insulating layer is formed on the silicon substrate. The plasma treatment layer is formed on the insulating layer. The metal electrode is formed on the portion of the plasma treatment layer. The sensing layer is formed on a surface of the metal electrode and the plasma treatment layer. Through plasma treatment for the substrate and printing graphene film on the substrate and the electrode, the adsorption characteristics of gas selection ratio for graphene is improved, and the processing time of the plasma treatment is adjusted to optimize the sensing characteristics.

Abstract: Light-addressable potentiometric sensing units are provided. A light-addressable potentiometric sensing unit comprises a conductive substrate, a metal oxide semiconductor layer, and a sensing layer. The metal oxide semiconductor layer is made of indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, indium oxide co-doped with tin and zinc, tin oxide, or zinc oxide. The wide-band gap characteristic of the metal oxide semiconductor layer enables the light-addressable potentiometric sensing unit to resist the interference from visible light. The light-addressable potentiometric sensing unit therefore exhibits a more stable performance.

Abstract: Light-addressable potentiometric sensing units are provided. A light-addressable potentiometric sensing unit comprises a conductive substrate, a metal oxide semiconductor layer, and a sensing layer. The metal oxide semiconductor layer is made of indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, indium oxide co-doped with tin and zinc, tin oxide, or zinc oxide. The wide-band gap characteristic of the metal oxide semiconductor layer enables the light-addressable potentiometric sensing unit to resist the interference from visible light. The light-addressable potentiometric sensing unit therefore exhibits a more stable performance.

Abstract: A Radio Frequency Identification (RFID) assembly includes an RFID reader/writer having a first micro-USB (Universal-Serial-Bus) connector and a mobile phone having a second micro-USB connector configured to electrically connect to the first micro-USB connector. In one embodiment of the present disclosure, the RFID reader/writer includes a circuit board having a first processor and a first USB controller, and an antenna board stacked on the circuit board, wherein the first USB controller electrically connects the first processor and the first micro-USB connector, and the antenna board includes a reverse F-shaped antenna. In one embodiment of the present disclosure, the mobile phone includes a second processor, and a second USB controller electrically connecting the second processor and the second micro-USB connector.

Abstract: A Radio Frequency Identification (RFID) assembly includes an RFID reader/writer having a first micro-USB (Universal-Serial-Bus) connector and a mobile phone having a second micro-USB connector configured to electrically connect to the first micro-USB connector. In one embodiment of the present disclosure, the RFID reader/writer includes a circuit board having a first processor and a first USB controller, and an antenna board stacked on the circuit board, wherein the first USB controller electrically connects the first processor and the first micro-USB connector, and the antenna board includes a reverse F-shaped antenna. In one embodiment of the present disclosure, the mobile phone includes a second processor, and a second USB controller electrically connecting the second processor and the second micro-USB connector.

Abstract: An umbrella structure with lighting device comprising a hollow shaft, a plurality of radial arranged stretchers mounted to the hollow shaft, a layer of fabric covered onto the stretchers, a light-emission device mounted at the tip of the hollow shaft, a handle connected at the bottom end of the hollow shaft, and a power supply device mounted with the handle, characterized in that the light-emission device comprises a light transmissive tube cover screwed at the tip of the hollow shaft, a light-emission body mounted within the tube cover, a fluorescent plate positioned between the light-emission body and the tube cover, and a stopper mounted at the top cover of the tube cover, the light emission body is lighted to flicker and the intensity of the emitted light is increased as a result of reflection and refraction by fluorescent body positioned within the fluorescent plate, the fluorescent light is emitted through the transparent tube cover to provide an alarming effect in the night.