Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: An image rendering device and an image rendering method are disclosed. For the elements of the image rendering device, a first sensor and a second sensor are configured to sense a target object in a two-dimensional (2D) mode and three-dimensional (3D) mode to generate a first surface-color-signal, a first 3D-depth-signal, a second surface-color-signal and a second 3D-depth-signal respectively. An IR projector is configured to generate an IR-dot-pattern. A processor is configured to control the IR projector to project the IR-dot-pattern on the target object in the 3D mode, and configured to process the first surface-color-signal, the second surface-color-signal, the first 3D-depth-signal and the second 3D-depth-signal to obtain a color 3D model of the target object.

Abstract: In an embodiment, a circuit includes: an error amplifier; a temperature sensor, wherein the temperature sensor is coupled to the error amplifier; a discrete time controller coupled to the error amplifier, wherein the discrete time controller comprises digital circuitry; a multiple bits quantizer coupled to the discrete time controller, wherein the multiple bits quantizer produces a digital code output; and a heating array coupled to the multiple bits quantizer, wherein the heating array is configured to generate heat based on the digital code output.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure. The method includes: forming a conformal layer over a first patterned layer over a substrate; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to form a second patterned layer and a patterned conformal layer; performing a second etching to remove a portion of the first patterned layer to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to remove a portion of the second patterned layer to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure. The method includes: forming a conformal layer over a first patterned layer over a substrate; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to form a second patterned layer and a patterned conformal layer; performing a second etching to remove a portion of the first patterned layer to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to remove a portion of the second patterned layer to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.

Abstract: A system for monitoring sleep efficiency includes a measuring device and a data processing device. The measuring device is for measuring body temperature of a subject and for outputting temperature data associated with the body temperature. The data processing device receives the temperature data, and is programmed to process the temperature data so as to determine sleep efficiency. The processing of the temperature data includes constructing a curve of the body temperature over asleep episode, finding a saddle point of the curve occurring for a first time, treating a time instance at which the saddle point occurs as a sleep-onset time point at which the subject falls asleep, and determining the sleep efficiency according to the sleep-onset time point.

Abstract: A system for monitoring sleep efficiency includes a measuring device and a data processing device. The measuring device is for measuring body temperature of a subject and for outputting temperature data associated with the body temperature. The data processing device receives the temperature data, and is programmed to process the temperature data so as to determine sleep efficiency. The processing of the temperature data includes constructing a curve of the body temperature over asleep episode, finding a saddle point of the curve occurring for a first time, treating a time instance at which the saddle point occurs as a sleep-onset time point at which the subject falls asleep, and determining the sleep efficiency according to the sleep-onset time point.

Abstract: A method includes rotating a wafer at a first speed for a first time duration. The wafer is rotated at a second speed that is lower than the first speed for a second time duration after the first time duration. The wafer is rotated at a third speed that is higher than the second speed for a third time duration after the second time duration. A photoresist is dispensed on the wafer during the first time duration and at least a portion of a time interval that includes the second time duration and the third time duration.

Abstract: In semiconductor fabrication processes, one or more wafers are often exposed to processes such as chemical vapor deposition to form semiconductor components thereupon. Often, some of the wafers exhibit flaws due to contamination or processing errors occurring before, during, or after component formation. Inspection of the wafers is often performed by direct visual inspection of humans, which is prone to errors due to flaws that are too small to view directly; to particles naturally arising in the human eye; and to fatigue caused by inspection of large numbers of wafers. Presented herein are inspection techniques involving positioning the wafer in a dark chamber exposing the surface of the wafer to a light source at a first angle, and capturing with a camera an image of the light source reflected from the surface of the wafer at a second angle. Wafers identified as exhibiting flaws are removed from the wafer set.

Abstract: Disclosure herein is related to a system for testing wireless signals and a method provided for establishing the system. One of the objectives is to establish one new testing system while the method effectively reduces the unstable problem caused by hardware or environmental variations. The testing system measures intensity of the wireless signals outputted from a device-under-test. While compared to a test signals, it is determined if the signal intensities there-between are balanced. Accordingly, the hardware of system is required to be adjusted. After that, the wireless signals are compared with sample signals for determining whether or not the test results are stable among the different testing system. An attenuation value may be introduced to adjusting the test result. A new testing system is therefore established.

Abstract: A method includes rotating a wafer at a first speed for a first time duration. The wafer is rotated at a second speed that is lower than the first speed for a second time duration after the first time duration. The wafer is rotated at a third speed that is higher than the second speed for a third time duration after the second time duration. A photoresist is dispensed on the wafer during the first time duration and at least a portion of a time interval that includes the second time duration and the third time duration.

Abstract: Disclosure herein is related to a system for testing wireless signals and a method provided for establishing the system. One of the objectives is to establish one new testing system while the method effectively reduces the unstable problem caused by hardware or environmental variations. The testing system measures intensity of the wireless signals outputted from a device-under-test. While compared to a test signals, it is determined if the signal intensities there-between are balanced. Accordingly, the hardware of system is required to be adjusted. After that, the wireless signals are compared with sample signals for determining whether or not the test results are stable among the different testing system. An attenuation value may be introduced to adjusting the test result. A new testing system is therefore established.

Abstract: In semiconductor fabrication processes, one or more wafers are often exposed to processes such as chemical vapor deposition to form semiconductor components thereupon. Often, some of the wafers exhibit flaws due to contamination or processing errors occurring before, during, or after component formation. Inspection of the wafers is often performed by direct visual inspection of humans, which is prone to errors due to flaws that are too small to view directly; to particles naturally arising in the human eye; and to fatigue caused by inspection of large numbers of wafers. Presented herein are inspection techniques involving positioning the wafer in a dark chamber exposing the surface of the wafer to a light source at a first angle, and capturing with a camera an image of the light source reflected from the surface of the wafer at a second angle. Wafers identified as exhibiting flaws are removed from the wafer set.

Abstract: A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.

Abstract: An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure.

Abstract: An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure.

Abstract: A one time programmable memory including a substrate, a plurality of isolation structures, a first transistor, and a second transistor is provided. The isolation structures are disposed in the substrate for defining an active area. A recess is formed on each of the isolation structures so that the top surface of the isolation structure is lower than that of the substrate. The first transistor is disposed on the active area of the substrate and is extended to the sidewall of the recess. The gate of the first transistor is a select gate. The second transistor is disposed on the active area of the substrate and is connected to the first transistor in series. The gate of the second transistor is a floating gate which is disposed across the substrate between the isolation structures in blocks and is extended to the sidewall of the recess.

Abstract: A method of manufacturing a non-volatile memory includes providing a substrate and forming a patterned mask layer, a tunnel dielectric layer, and a first conductive layer on the substrate. The first conductive layer on the mask layer is removed to form second conductive layers disposed on the sidewall of the mask layer and the substrate. The mask layer is then removed and a source region is formed. Subsequently, an inter-gate dielectric layer and a third conductive layer are formed on the substrate. The third conductive layer is patterned to cover the source region and a portion of the second conductive layer on both sides of the source region. A portion of the inter-gate dielectric layer and the second conductive layers are then removed. After that, a dielectric layer, a fourth conductive layer, and a drain region are formed, respectively.

Abstract: A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.