Patents by Inventor Tsung-Da Lin
Tsung-Da Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240142428Abstract: A water quality detection device including a detection tank, a sensor, the cleaner and a processor is provided. The sensor is disposed on the detection tank and is configured to sense a to-be-detected liquid within the detection tank. The cleaner is configured to clean the sensor. The processor is electrically connected to the sensor and the cleaner and is configured to: execute an initialization procedure, which includes driving the sensor to sense the to-be-detected liquid to obtain a number of initial sensing values and calculating a threshold value according to the initial sensing values; drive the sensor to sense the to-be-detected liquid to obtain a sensing value of the to-be-detected liquid, and determine whether the sensing value of the to-be-detected liquid reaches the threshold value; drive the cleaner to operate when the sensing value of the to-be-detected liquid reaches the threshold value.Type: ApplicationFiled: February 17, 2023Publication date: May 2, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsung-Yu TSAI, Hung-Sheng LIN, Cheng-Da KO, Chun-Te CHUANG
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Publication number: 20240071767Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.Type: ApplicationFiled: January 6, 2023Publication date: February 29, 2024Inventors: Hsueh-Ju Chen, Chi On Chui, Tsung-Da Lin, Pei Ying Lai, Chia-Wei Hsu
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Publication number: 20230378294Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Inventors: Chia-Yuan Chang, Te-Yang Lai, Kuei-Lun Lin, Xiong-Fei Yu, Chi On Chui, Tsung-Da Lin, Cheng-Hao Hou
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Publication number: 20230369124Abstract: A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Te-Yang Lai, Hsueh-Ju Chen, Tsung-Da Lin, Chi On Chui
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Patent number: 11791216Abstract: A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.Type: GrantFiled: January 12, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Te-Yang Lai, Hsueh-Ju Chen, Tsung-Da Lin, Chi On Chui
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Publication number: 20230317523Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first fin structure over a first region of a substrate and forming a second fin structure over a second region of a substrate, forming a first gate dielectric layer around the first fin structure and forming a second gate dielectric layer around the second fin structure, forming a barrier layer over the first gate dielectric layer, treating the substrate with a first fluorine-containing gas, forming a work function layer over the second gate dielectric layer after treating the substrate with the first fluorine-containing gas, and treating the substrate with a second fluorine-containing gas after forming the work function layer over the second gate dielectric layer.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei Ying LAI, Chia-Wei HSU, Tsung-Da LIN, Chi On CHUI
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Publication number: 20230238241Abstract: A method includes forming a dummy gate stack on a semiconductor region, forming gate spacers on sidewalls of the dummy gate stack, removing the dummy gate stack to form a recess between the gate spacers, and forming a silicon oxide layer on the semiconductor region. The silicon oxide layer extends into the recess. A high-k dielectric layer is deposited over the silicon oxide layer, and a silicon layer is deposited over the high-k dielectric layer. The silicon layer extends into the recess. The high-k dielectric layer and the silicon layer are in-situ deposited in a same vacuum environment. The method further includes performing an annealing process on the silicon layer and the high-k dielectric layer, removing the silicon layer, and forming a gate electrode over the high-k dielectric layer. The gate electrode fills the recess.Type: ApplicationFiled: May 12, 2022Publication date: July 27, 2023Inventors: Jyun-Yi Wu, Chung-Yi Su, Tsung-Da Lin, Chi On Chui
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Publication number: 20230223439Abstract: An embodiment includes a device including a first high-k gate dielectric on a first channel region of a first semiconductor feature, the first high-k gate dielectric being a crystalline layer with a grain size in a range of 10 ? to 200 ?. The device also includes a first gate electrode on the first high-k gate dielectric. The device also includes a source region and a drain region on opposite sides of the first gate electrode.Type: ApplicationFiled: April 7, 2022Publication date: July 13, 2023Inventors: Te-Yang Lai, Chun-Yen Peng, Tsung-Da Lin, Chi On Chui
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Publication number: 20230178601Abstract: In an embodiment, a semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and a second dipole dopant. The first dipole dopant along a thickness direction of the first gate dielectric layer has a first concentration peak, and the second dipole dopant along the thickness direction of the first gate dielectric layer has a second concentration peak. The second concentration peak is located between the first concentration peak and an upper surface of the first gate dielectric layer. The second concentration peak is offset from the upper surface of the first gate dielectric layer.Type: ApplicationFiled: June 3, 2022Publication date: June 8, 2023Inventors: Te-Yang Lai, Hsueh-Ju Chen, Tsung-Da Lin, Chi On Chui
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Publication number: 20230115634Abstract: In an embodiment, a method includes: forming a gate dielectric layer on a channel region of a semiconductor feature; depositing a work function tuning layer on the gate dielectric layer, the work function tuning layer including a first work function tuning element; depositing a capping layer on the work function tuning layer with atomic layer deposition, the capping layer formed of an oxide or a nitride; performing an anneal process while the capping layer covers the work function tuning layer, the anneal process driving the first work function tuning element from the work function tuning layer into the gate dielectric layer; removing the capping layer to expose the work function tuning layer; and depositing a fill layer on the work function tuning layer.Type: ApplicationFiled: May 3, 2022Publication date: April 13, 2023Inventors: Tsung-Da Lin, Chia-Wei Hsu, Chi On Chui
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Publication number: 20230063857Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen
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Publication number: 20220285160Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The method includes depositing a gate dielectric layer over the insulating layer and in the wide trench and the narrow trench using an atomic layer deposition process. The method includes forming a gate electrode layer over the gate dielectric layer. The method includes removing the gate dielectric layer and the gate electrode layer outside of the wide trench and the narrow trench.Type: ApplicationFiled: July 13, 2021Publication date: September 8, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Lun LIN, Yen-Fu CHEN, Da-Yuan LEE, Tsung-Da LIN, Chi On CHUI
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Publication number: 20220084889Abstract: A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.Type: ApplicationFiled: January 12, 2021Publication date: March 17, 2022Inventors: Te-Yang Lai, Hsueh-Ju Chen, Tsung-Da Lin, Chi On Chui
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Publication number: 20210399104Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.Type: ApplicationFiled: April 15, 2021Publication date: December 23, 2021Inventors: Chia-Yuan Chang, Te-Yang Lai, Kuei-Lun Lin, Xiong-Fei Yu, Chi On Chui, Tsung-Da Lin, Cheng-Hao Hou
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Patent number: 10964543Abstract: Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an embodiment, a method includes conformally forming a gate dielectric layer on a fin extending from a substrate and along sidewalls of gate spacers over the fin, conformally depositing a dummy layer over the gate dielectric layer during a deposition process using a silicon-containing precursor and a dopant gas containing fluorine, deuterium, or a combination thereof, the dummy layer as deposited comprising a dopant of fluorine, deuterium, or a combination thereof, performing a thermal process to drive the dopant from the dummy layer into the gate dielectric layer, removing the dummy layer, and forming one or more metal-containing layers over the gate dielectric layer.Type: GrantFiled: November 4, 2019Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Da Lin, Che-Hao Chang, Cheng-Hao Hou, Xiong-Fei Yu
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Publication number: 20200066535Abstract: Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby.Type: ApplicationFiled: November 4, 2019Publication date: February 27, 2020Inventors: Tsung-Da Lin, Che-Hao Chang, Cheng-Hao Hou, Xiong-Fei Yu
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Patent number: 10468258Abstract: Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an embodiment, a method includes conformally forming a gate dielectric layer on a fin extending from a substrate and along sidewalls of gate spacers over the fin, conformally depositing a dummy layer over the gate dielectric layer during a deposition process using a silicon-containing precursor and a dopant gas containing fluorine, deuterium, or a combination thereof, the dummy layer as deposited comprising a dopant of fluorine, deuterium, or a combination thereof, performing a thermal process to drive the dopant from the dummy layer into the gate dielectric layer, removing the dummy layer, and forming one or more metal-containing layers over the gate dielectric layer.Type: GrantFiled: June 12, 2018Date of Patent: November 5, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Da Lin, Che-Hao Chang, Cheng-Hao Hou, Xiong-Fei Yu
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Patent number: 8859441Abstract: The present invention provides a system and method for manufacturing a semiconductor device including a substrate and a high-? dielectric layer on the substrate. The system comprises a modular track; a substrate-forming chamber connected with the modular track for forming the substrate; and an atomic layer deposition (ALD) chamber connected with the modular track for providing the high-? dielectric layer.Type: GrantFiled: April 5, 2012Date of Patent: October 14, 2014Inventors: Ming-Hwei Hong, Ray-Nien Kwo, Tun-Wen Pi, Mao-Lin Huang, Yu-Hsing Chang, Pen Chang, Chun-An Lin, Tsung-Da Lin
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Publication number: 20130267077Abstract: The present invention provides a system and method for manufacturing a semiconductor device including a substrate and a high-? dielectric layer on the substrate. The system comprises a modular track; a substrate-forming chamber connected with the modular track for forming the substrate; and an atomic layer deposition (ALD) chamber connected with the modular track for providing the high-? dielectric layer.Type: ApplicationFiled: April 5, 2012Publication date: October 10, 2013Inventors: Ming-Hwei Hong, Ray-Nien Kwo, Tun-Wen Pi, Mao-Lin Huang, Yu-Hsing Chang, Pen Chang, Chun-An Lin, Tsung-Da Lin
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Patent number: 7658284Abstract: A socket retaining assembly includes a retaining assembly having a seat, and a retaining post; the retaining post being installed at an upper end of the stopper; an outer periphery of the retaining post being installed with a confining projection and a plurality of trenches; a combination unit including a rotating assembly and a push unit; the stopper serving to confine the rotation range of the combination unit; the rotating assembly has a C ring at a lower end thereof two ends of an opening of the C ring being concaved inwards so as to form with inward projections; an upper side of the C ring being installed with a rectangular protruding block; an interior of the protruding block being formed with a rectangular receiving groove; and the push unit being installed in the receiving groove of the protruding block.Type: GrantFiled: June 28, 2007Date of Patent: February 9, 2010Inventor: Tsung-Da Lin