Abstract: An inductor is disclosed, the inductor comprising: a T-shaped magnetic core, being made of a material comprising an annealed soft magnetic metal material and having a base and a pillar integrally formed with the base, wherein ?C×Hsat?1800, where ?C is a permeability of the T-shaped magnetic core, and Hsat (Oe) is a strength of the magnetic field at 80% of ?C0, where ?C0 is the permeability of the T-shaped magnetic core when the strength of the magnetic field is 0.

Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.

Abstract: A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.

Abstract: In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is W1 compared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is W2 when W1>W2.

Abstract: In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is W1 compared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is W2 when W1>W2.

Abstract: In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is W1 compared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is W2 when W1>W2.

Abstract: A method of inspecting power units applied to a plurality of power units is connected to a signal bus. The method is to disconnect the power unit having an output current from the signal bus, give a control command by a controller for raising the output current, measure the output current after the control command is given, and compare the measured output current with the target current value corresponding to the control command for determining an inspection result. The present disclosed example can effectively reduce inspection time and improve inspection accuracy.

Abstract: A method of inspecting power units applied to a plurality of power units is connected to a signal bus. The method is to disconnect the power unit having an output current from the signal bus, give a control command by a controller for raising the output current, measure the output current after the control command is given, and compare the measured output current with the target current value corresponding to the control command for determining an inspection result. The present disclosed example can effectively reduce inspection time and improve inspection accuracy.

Abstract: A lithography system is provided and includes a light source device configured to emit a processing light beam onto the semiconductor wafer, to generate a penetrating light beam and a reflected light beam. The lithography system further includes a detecting module having a first detector and a second detector. The first detector is configured to receive the penetrating light beam to generate first power data, and the second detector is configured to receive the reflected light beam to generate second power data. The lithography system also includes a monitoring device configured to calculate absorbed power data of the semiconductor wafer according to the first power data, the second power data and reference power data of a reference light beam and configured to compensate for a pattern formed on the semiconductor wafer resulting from the processing light beam according to the absorbed power data and reference information.

Abstract: A lithography system is provided and includes a light source device configured to emit a processing light beam onto the semiconductor wafer, to generate a penetrating light beam and a reflected light beam. The lithography system further includes a detecting module having a first detector and a second detector. The first detector is configured to receive the penetrating light beam to generate first power data, and the second detector is configured to receive the reflected light beam to generate second power data. The lithography system also includes a monitoring device configured to calculate absorbed power data of the semiconductor wafer according to the first power data, the second power data and reference power data of a reference light beam and configured to compensate for a pattern formed on the semiconductor wafer resulting from the processing light beam according to the absorbed power data and reference information.

Abstract: A substrate structure is provided. The substrate structure includes a number of traces, a substrate core, a number of first metal tiles, a number of second metal tiles, a number of first electrically-functioning circuits, and a number of second electrically-functioning circuits. The substrate core has a first surface and a second surface opposite to the first surface. The traces, the first metal tiles, and the first electrically-functioning circuits are disposed on the first surface and add up to a first metal structure proportion, and the second metal tiles and the second electrically-functioning circuits are disposed on the second surface and add up to a second metal structure proportion. The difference between the first metal structure proportion and the second metal structure proportion is within 15%.

Abstract: A system includes a wafer stage adapted to hold a semiconductor wafer thereon. A moveable temperature sensor array is configured to move to a plurality of different positions over a surface of the wafer stage and to take a plurality of temperature measurements at the plurality of positions, respectively. Based on the plurality of temperature measurements, a controller is adapted to determine an expected thermal deformation for the semiconductor wafer or for a reticle arranged over the semiconductor wafer.

Abstract: A system includes a wafer stage adapted to hold a semiconductor wafer thereon. A moveable temperature sensor array is configured to move to a plurality of different positions over a surface of the wafer stage and to take a plurality of temperature measurements at the plurality of positions, respectively. Based on the plurality of temperature measurements, a controller is adapted to determine an expected thermal deformation for the semiconductor wafer or for a reticle arranged over the semiconductor wafer.

Abstract: A substrate structure is provided. The substrate structure includes a number of traces, a substrate core, a number of first metal tiles, a number of second metal tiles, a number of first electrically-functioning circuits, and a number of second electrically-functioning circuits. The substrate core has a first surface and a second surface opposite to the first surface. The traces, the first metal tiles, and the first electrically-functioning circuits are disposed on the first surface and add up to a first metal structure proportion, and the second metal tiles and the second electrically-functioning circuits are disposed on the second surface and add up to a second metal structure proportion. The difference between the first metal structure proportion and the second metal structure proportion is within 15%.

Abstract: A substrate structure and a package structure using the same are provided. The substrate structure includes a number of traces, a substrate core and a number of first metal tiles. The substrate core has a first surface and a second surface opposite to the first surface. The first metal tiles are disposed on one of the first surface and the second surface, the minimum pitch between adjacent two of the first metal tiles is the minimum process pitch.

Abstract: A substrate structure and a package structure using the same are provided. The substrate structure includes a number of traces, a substrate core and a number of first metal tiles. The substrate core has a first surface and a second surface opposite to the first surface. The first metal tiles are disposed on one of the first surface and the second surface, the minimum pitch between adjacent two of the first metal tiles is the minimum process pitch.