Patents by Inventor Tsung-Hua Yang
Tsung-Hua Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240182141Abstract: A multihull module is provided. The multihull module includes multiple power floats, an actuation interface controller, and a vehicle controller. The power floats are disposed on a vehicle. The actuation interface controller is coupled to the power floats, and is configured to control the power floats. The vehicle controller is coupled to the actuation interface controller, and is configured to provide a control signal to the actuation interface controller. The actuation interface controller controls the power floats according to the control signal.Type: ApplicationFiled: December 6, 2022Publication date: June 6, 2024Applicant: Metal Industries Research & Development CentreInventors: Kuang-Shine Yang, Chao Chieh Hsu, Ping-Hua Su, Tsung-Yi Lan, Chia-Yu Hung
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Patent number: 12002883Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first depressed top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.Type: GrantFiled: January 18, 2022Date of Patent: June 4, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tsung-Yu Yang, Shin-Hung Li, Ruei-Jhe Tsao, Che-Hua Chang
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Patent number: 11983680Abstract: An intelligent monitoring system for waste disposal and the method thereof are provided, which include a plurality of operational devices and stages. First, a transportation stage is performed to loading a transport vehicle with a waste so as to transport the waste to a disposal station for further treatment. A camera and a sensor for detecting abnormal conditions are installed any one of the operational devices or installed in the operational path of any one of the operational devices. The camera records the videos of the operational stages, captures the images from the videos and recognizes the images in order to determine whether the abnormal conditions occur in any one of the operational stages. Alternatively, the camera is triggered to capture the images and recognize the images after the abnormal conditions are detected by the sensor in order to determine whether the abnormal conditions actually occur.Type: GrantFiled: June 12, 2021Date of Patent: May 14, 2024Assignee: CHASE SUSTAINABILITY TECHNOLOGY CO., LTD.Inventors: Yung-Fa Yang, Tsung-Tien Chen, Shao-Hsin Hsu, Bo-Wei Chen, Chia-Ching Chen, Ming-Hua Tang
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Patent number: 11950424Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.Type: GrantFiled: June 7, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Ting Tsai, Ching-Tzer Weng, Tsung-Hua Yang, Kao-Chao Lin, Chi-Wei Ho, Chia-Ta Hsieh
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Patent number: 11948971Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.Type: GrantFiled: August 10, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Wei Yu, Tsz-Mei Kwok, Tsung-Hsi Yang, Li-Wei Chou, Ming-Hua Yu
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Patent number: 11927303Abstract: A wearable device includes a host, a first belt, a second belt, a circuit board, a cable, and an adjustment mechanism. The first belt, one end of which is connected to a first side of the host, has a cable holding part. One end of the second belt is connected to a second side of the host. The circuit board is disposed at an overlap of the first belt and the second belt. A first end and a second end opposite to each other of the cable are connected to the circuit board and the first side respectively, and a holding section of the cable is fixed to the cable holding part. The adjusting mechanism is disposed at an overlap of the first belt and the second belt to adjust an overlapping length of the first belt and the second belt.Type: GrantFiled: July 25, 2022Date of Patent: March 12, 2024Assignee: HTC CorporationInventors: Tsen-Wei Kung, Chung-Ju Wu, Tsung Hua Yang, Chih-Yao Chang, Wei Te Tu
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Patent number: 11798836Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.Type: GrantFiled: June 17, 2021Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Yu Yang, Po-Wei Liu, Yun-Chi Wu, Yu-Wen Tseng, Chia-Ta Hsieh, Ping-Cheng Li, Tsung-Hua Yang, Yu-Chun Chang
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Publication number: 20230280020Abstract: A wearable device and a head strap module are provided. The wearable device includes a host and a head strap module. Two opposite sides of the host are provided with a first bracket and a second bracket. The first bracket has a first end. The second bracket has a second end. The head strap module includes a first belt, a second belt, and an adjustment mechanism. The first belt has a third end. The second belt has a fourth end. The third end and the fourth end are detachably assembled to the first end and the second end respectively. The adjustment mechanism is arranged at the overlapping position of the first belt and the second belt for adjusting the overlapping length of the first belt and the second belt.Type: ApplicationFiled: July 25, 2022Publication date: September 7, 2023Applicant: HTC CorporationInventors: Tsen-Wei Kung, Chung-Ju Wu, Tsung Hua Yang, Chih-Yao Chang, Wei Te Tu
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Publication number: 20230279989Abstract: A wearable device includes a host, a first belt, a second belt, a circuit board, a cable, and an adjustment mechanism. The first belt, one end of which is connected to a first side of the host, has a cable holding part. One end of the second belt is connected to a second side of the host. The circuit board is disposed at an overlap of the first belt and the second belt. A first end and a second end opposite to each other of the cable are connected to the circuit board and the first side respectively, and a holding section of the cable is fixed to the cable holding part. The adjusting mechanism is disposed at an overlap of the first belt and the second belt to adjust an overlapping length of the first belt and the second belt.Type: ApplicationFiled: July 25, 2022Publication date: September 7, 2023Applicant: HTC CorporationInventors: Tsen-Wei Kung, Chung-Ju Wu, Tsung Hua Yang, Chih-Yao Chang, Wei Te Tu
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Publication number: 20230275131Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.Type: ApplicationFiled: May 3, 2023Publication date: August 31, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wen TSENG, Po-Wei LIU, Hung-Ling SHIH, Tsung-Yu YANG, Tsung-Hua YANG, Yu-Chun CHANG
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Patent number: 11670689Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.Type: GrantFiled: September 10, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wen Tseng, Po-Wei Liu, Hung-Ling Shih, Tsung-Yu Yang, Tsung-Hua Yang, Yu-Chun Chang
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Publication number: 20220406652Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.Type: ApplicationFiled: June 17, 2021Publication date: December 22, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Yu YANG, Po-Wei LIU, Yun-Chi WU, Yu-Wen TSENG, Chia-Ta HSIEH, Ping-Cheng LI, Tsung-Hua YANG, Yu-Chun CHANG
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Publication number: 20220392912Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Inventors: Yu-Ting Tsai, Ching-Tzer Weng, Tsung-Hua Yang, Kao-Chao Lin, Chi-Wei Ho, Chia-Ta Hsieh
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Publication number: 20220359671Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.Type: ApplicationFiled: September 10, 2021Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wen TSENG, Po-Wei LIU, Hung-Ling SHIH, Tsung-Yu YANG, Tsung-Hua YANG, Yu-Chun CHANG
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Patent number: 11121047Abstract: A semiconductor structure includes a substrate, a device, a contact via, a metal/dielectric layer, and a test structure. The device is over the substrate. The contact via is connected to the device. The metal/dielectric layer is over the contact via. The metal/dielectric layer includes a first portion and a second portion. The first portion of the metal/dielectric layer has a metallization pattern connected to the contact via. The second portion of the metal/dielectric layer is void of metal. The test structure is over the second portion of the metal/dielectric layer.Type: GrantFiled: March 14, 2019Date of Patent: September 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Bo Shu, Tsung-Hua Yang, Chung-Jen Huang
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Publication number: 20200294871Abstract: A semiconductor structure includes a substrate, a device, a contact via, a metal/dielectric layer, and a test structure. The device is over the substrate. The contact via is connected to the device. The metal/dielectric layer is over the contact via. The metal/dielectric layer includes a first portion and a second portion. The first portion of the metal/dielectric layer has a metallization pattern connected to the contact via. The second portion of the metal/dielectric layer is void of metal. The test structure is over the second portion of the metal/dielectric layer.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Inventors: Cheng-Bo SHU, Tsung-Hua YANG, Chung-Jen HUANG
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Patent number: 9042000Abstract: A flexible liquid crystal display and a flexible fluid display are provided. The flexible liquid crystal display includes a first module, a second module, at least two supporting structures and a liquid crystal layer. The second module is disposed correspondingly to the first module. The supporting structures are separately disposed between the first module and the second module and used for abutting the first module and the second module, so that a space between the first module and the second module is divided into a flexible area and two non-flexible areas. The flexible area is located between the two non-flexible areas. The liquid crystal layer is disposed in the flexible area and the two non-flexible areas.Type: GrantFiled: May 27, 2014Date of Patent: May 26, 2015Assignee: WISTRON CORPORATIONInventors: Tarng-Shiang Hu, Yi-Kai Wang, Yu-Jung Peng, Tsung-Hua Yang, Chih-Hao Chang
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Publication number: 20150004546Abstract: A method for fabricating a photo spacer and an array substrate having the photo spacer are provided. At least one exposure process, a developing process, and a baking process are performed to a photo-sensitive material layer formed a substrate to fabricate a photo spacer, wherein the at least one exposure process includes a back side exposure process. The substrate has a light transmitting region and a light shielding region so that the photo-sensitive material layer is defined into a first block and a second block after the back side exposure process. The developing process is performed to at least remove the second block. A front side exposure process is performed to the first block. The baking process is performed to cure the first block of the photo-sensitive material layer to form a photo spacer.Type: ApplicationFiled: September 16, 2014Publication date: January 1, 2015Inventors: Yi-Kai Wang, Tarng-Shiang Hu, Tsung-Hua Yang, Yu-Jung Peng, Chih-Hao Chang
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Publication number: 20140268297Abstract: A flexible liquid crystal display and a flexible fluid display are provided. The flexible liquid crystal display includes a first module, a second module, at least two supporting structures and a liquid crystal layer. The second module is disposed correspondingly to the first module. The supporting structures are separately disposed between the first module and the second module and used for abutting the first module and the second module, so that a space between the first module and the second module is divided into a flexible area and two non-flexible areas. The flexible area is located between the two non-flexible areas. The liquid crystal layer is disposed in the flexible area and the two non-flexible areas.Type: ApplicationFiled: May 27, 2014Publication date: September 18, 2014Applicant: Wistron CorporationInventors: Tarng-Shiang Hu, Yi-Kai Wang, Yu-Jung Peng, Tsung-Hua Yang, Chih-Hao Chang
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Patent number: 8804065Abstract: A flexible liquid crystal display and a flexible fluid display are provided. The flexible liquid crystal display includes a first module, a second module, at least two supporting structures and a liquid crystal layer. The second module is disposed correspondingly to the first module. The supporting structures are separately disposed between the first module and the second module and used for abutting the first module and the second module, so that a space between the first module and the second module is divided into a flexible area and two non-flexible areas. The flexible area is located between the two non-flexible areas. The liquid crystal layer is disposed in the flexible area and the two non-flexible areas.Type: GrantFiled: January 9, 2012Date of Patent: August 12, 2014Assignee: Wistron CorporationInventors: Tarng-Shiang Hu, Yi-Kai Wang, Yu-Jung Peng, Tsung-Hua Yang, Chih-Hao Chang