Patents by Inventor Tsung-Ju CHEN
Tsung-Ju CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12001248Abstract: A hinge structure applied to an electronic device having a first component and a second component is provided. The hinge structure includes a torque hinge and a one-way pivoting mechanism. The torque hinge includes a first base and a first rotation element. The first base connects to the first component. The first rotation element rotatably connects to the first base. The second component pivotally connects to the first rotation element through the one-way pivoting mechanism.Type: GrantFiled: May 28, 2021Date of Patent: June 4, 2024Assignee: ASUSTEK COMPUTER INC.Inventors: Tsung-Ju Chiang, Marco Da Ros, Yung-Hsiang Chen, Li Wei Hung
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Patent number: 11990509Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.Type: GrantFiled: July 18, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
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Publication number: 20240145250Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.Type: ApplicationFiled: January 12, 2024Publication date: May 2, 2024Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
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Publication number: 20240117837Abstract: A foldable electronic device includes a first body, a second body, a first hinge module, a second hinge module, a driving sheet, and a one-way bearing. The first body has a display surface and a back surface. The first hinge module has a first shaft pivotally connected to the first body and a second shaft pivotally connected to the second body. The second shaft has a virtual axis. The second hinge module is disposed to the second body and has a rotating shaft. The rotating shaft is disposed corresponding to the virtual axis. The driving sheet is located between the first shaft and the second shaft, and is located between the first hinge module and the second hinge module. The one-way bearing is rotatably disposed around the rotating shaft. The one-way bearing has a bearing stop portion corresponding to the driving sheet.Type: ApplicationFiled: April 24, 2023Publication date: April 11, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Tsung-Ju Chiang, Yung-Hsiang Chen
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Patent number: 11944659Abstract: The invention provides a method for improving sarcopenia of a subject in need thereof by using Phellinus linteus, in which the method includes administering an effective dose of composition to the subject, and the composition includes Phellinus linteus (NITE BP-03321 and BCRC 930210) as an effective substance. By using the aforementioned composition including an extract of a fermented product of the Phellinus linteus and/or its derivative, diameters of myotubes, amounts of muscles and muscle muscular endurance can be maintained, thereby improving sarcopenia.Type: GrantFiled: October 12, 2021Date of Patent: April 2, 2024Assignee: GRAPE KING BIO LTDInventors: Chin-Chu Chen, I-Chen Li, Tsung-Ju Li, Ting-Yu Lu, Yen-Po Chen
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Patent number: 11946945Abstract: A sample analyzing method and a sample preparing method are provided. The sample analyzing method includes a sample preparing step, a placing step, and an analyzing step. The sample preparing step includes an obtaining step implemented by obtaining an identification information; and a marking and placing step implemented by placing a sample carrying component having a sample disposed thereon into a marking equipment, allowing the marking equipment to utilize the identification information to form an identification structure on the sample carrying component, and placing the sample carrying component into one of the accommodating slots according to the identification information. The placing step is implemented by taking out the sample carrying component from one of the accommodating slots and placing the sample carrying component into an electron microscope equipment. The analyzing step is implemented by utilizing the electron microscope equipment to photograph the sample to generate an analyzation image.Type: GrantFiled: July 29, 2021Date of Patent: April 2, 2024Assignee: MATERIALS ANALYSIS TECHNOLOGY INC.Inventors: Keng-Chieh Chu, Tsung-Ju Chan, Chun-Wei Wu, Hung-Jen Chen
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Publication number: 20240071767Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.Type: ApplicationFiled: January 6, 2023Publication date: February 29, 2024Inventors: Hsueh-Ju Chen, Chi On Chui, Tsung-Da Lin, Pei Ying Lai, Chia-Wei Hsu
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Patent number: 11908695Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.Type: GrantFiled: July 16, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
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Publication number: 20230274938Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer as formed includes silicon oxide, and the nitridation operation comprises a plasma nitridation operation using a N2 gas and a NH3 gas.Type: ApplicationFiled: June 10, 2022Publication date: August 31, 2023Inventors: Hao-Ming TANG, Shu-Han CHEN, Yun-San CHIEN, Da-Yuan LEE, Chi On CHUI, Tsung-Ju CHEN, Yi-Hsin TING, Han-Shen WANG
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Publication number: 20230126442Abstract: A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.Type: ApplicationFiled: May 9, 2022Publication date: April 27, 2023Inventors: Tsung-Ju Chen, Shu-Han Chen, Chun-Heng Chen, Chi On Chui
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Publication number: 20220352313Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
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Patent number: 11430865Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.Type: GrantFiled: May 22, 2020Date of Patent: August 30, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
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Patent number: 11393900Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.Type: GrantFiled: May 22, 2020Date of Patent: July 19, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
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Publication number: 20210343533Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
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Publication number: 20210233997Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.Type: ApplicationFiled: May 22, 2020Publication date: July 29, 2021Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
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Patent number: 11069531Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.Type: GrantFiled: July 2, 2019Date of Patent: July 20, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
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Publication number: 20200135474Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.Type: ApplicationFiled: July 2, 2019Publication date: April 30, 2020Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
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Patent number: 9939353Abstract: An apparatus for cell observation and a method for cell collection using the same are disclosed. The apparatus for cell selection comprises a first substrate having an opening; and a second substrate having a photoresist unit disposed on a surface thereof, wherein the photoresist unit comprises at least one notch and defines a space which is interconnected with the notch and corresponds to the opening of the first substrate.Type: GrantFiled: March 25, 2015Date of Patent: April 10, 2018Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Fan-Gang Tseng, Jui-Chia Chang, Tsung-Ju Chen
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Publication number: 20160061710Abstract: An apparatus for cell observation and a method for cell collection using the same are disclosed. The apparatus for cell selection comprises a first substrate having an opening; and a second substrate having a photoresist unit disposed on a surface thereof, wherein the photoresist unit comprises at least one notch and defines a space which is interconnected with the notch and corresponds to the opening of the first substrate.Type: ApplicationFiled: March 25, 2015Publication date: March 3, 2016Inventors: Fan-Gang TSENG, Jui-Chia CHANG, Tsung-Ju CHEN
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Publication number: 20140045254Abstract: A cell self-assembly array chip comprises a first substrate, a second substrate and a plurality of spacer elements. The first substrate, the spacer elements and the second substrate are stacked to be one in turn, wherein the spacer elements are annularly arranged at interval and disposed on the second substrate, so as to define a cell self-assembly region and at least one drawing channel. Furthermore, because the liquid portion of cell suspension horizontally and radially passed the drawing channel outward and the radially outward pulling force generated by the evaporation effect of the liquid portion, so as to cause the cells are arranged by the cell self-assembly array to the cell self-assembly region. The present invention further provides a manufacturing method of a cell self-assembly array chip to solve the conventional problems which is difficult to culture living cells and not easy to apply optical observation.Type: ApplicationFiled: December 21, 2012Publication date: February 13, 2014Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Fan-Gang TSENG, Tsung-Ju CHEN, Yu-Cheng CHANG