Abstract: An electronic device includes a rollable panel and a metal layer. The rollable panel includes a first portion and a second portion. The rollable panel has a first side and a second side opposite to the first side. The rollable panel includes a substrate, a circuit layer disposed on the substrate and a cover layer disposed on the circuit layer. The metal layer is disposed on one of the first side and the second side of the rollable panel and outside the rollable panel. In a rolled mode, at least a part of the metal layer is positioned between the first portion and the second portion of the rollable panel.

Abstract: An electronic device includes a substrate, a semiconductor unit and an insulating layer. The semiconductor unit is disposed on the substrate. The insulating layer is disposed on the semiconductor unit, and the insulating layer includes a first portion and a second portion connected to the first portion. In a top view, the first portion partially overlaps the semiconductor unit, the second portion does not overlap the semiconductor unit, and a part of an edge of the insulating layer is irregular.

Abstract: A display device includes a display panel including a rollable portion and a non-rollable portion. The display panel includes a supporting structure including a groove disposed on a first side of the supporting structure, a substrate disposed on a second side of the supporting structure and the first side opposite to the second side, and a circuit board fixed onto a back of the display panel. The non-rollable portion has a first region. A first region of the circuit board is joined to the first region of the non-rollable portion. The non-rollable portion has a first end and a second end. The first end is connected to the rollable portion. The second end is connected to the circuit board.

Abstract: The disclosure provides a transparent display device including a display panel. The display panel includes a display area, a non-display area, and a plurality of pixels. The non-display area is adjacent to the display area. The plurality of pixels are disposed in the display area. A difference between a transmittance of the display area and a transmittance of the non-display area is less than 30% of the transmittance of the display area.

Abstract: An electronic assembly is provided. The electronic assembly includes a first circuit structure including a conductive structure, a second circuit structure disposed on the first circuit structure, a plurality of electronic elements disposed on the first circuit structure, and a connecting element disposed on the first circuit layer. The connecting element is disposed between two adjacent ones of the plurality electronic elements and electrically connected to the second circuit layer and one of the two adjacent ones of the plurality of electronic elements.

Abstract: Disclosed is a bio sensing device including a medium layer, a light emitting element and an optical sensor. The light emitting element is configured to emit a light toward a user's skin layer, in which the light passes through the medium layer and has a maximum intensity in a first wavelength. The optical sensor is configured to receive a reflected part of the light from the user's skin layer, in which the reflected part of the light passes through the medium layer, and the medium layer has a first transmittance greater than 60% with respect to the first wavelength.

Abstract: An electronic device and an electronic device operation method are disposed. The electronic device includes a flexible element and a controller. The flexible element includes a plurality of sensing electrodes. In a stacked state, a first portion of the flexible element overlaps a second portion of the flexible element. The controller is electrically connected to the plurality of the sensing electrodes of the flexible element. The controller receives a first signal from the plurality of sensing electrodes in the first portion and receives a second signal from the plurality of the sensing electrodes in the second portion.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: The disclosure provides a display device. The display device includes a display panel and a vibration generating module. The vibration generating module is attached to the display panel and includes a substrate, a circuit layer, and a plurality of vibrators. The circuit layer and the plurality of vibrators are disposed on the substrate, and the plurality of vibrators are electrically connected to the circuit layer.

Abstract: A display device includes a patterned substrate, a plurality of light emitting unit, a first insulating layer and a sensing layer. The patterned substrate has a plurality of island structures and a plurality of bridge structures, and at least one bridge structure connects two adjacent island structures. At least one light emitting unit is disposed on one of the two adjacent island structures. The first insulating layer is disposed on the light emitting units. The sensing layer is disposed on the first insulating layer and has a mesh unit, the mesh unit has a mesh frame and an opening, and the at least one light emitting unit is disposed in the opening.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.

Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.

Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.

Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.

Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.

Abstract: A dispatching method and system based on multiple levels of steady state production rate in working benches are provided. The dispatching method includes the following steps: receiving a plurality of real-time streaming data regarding a plurality of products being produced by a plurality of productive working benches; grouping the production rate values comprised in each real-time streaming data according to a first data binning technique, so as to produce a first steady state production rate value corresponding to each real-time streaming data; grouping the production rate values comprised in each real-time streaming data according to a second data binning technique, so as to produce a second steady state production rate value corresponding to each real-time streaming data; and determining a dispatching message of a to-be-produced product according to a portion of the first steady state production rate values and a portion of the second steady state production rate values.

Abstract: An automatically brightness adjusting electronic device and a brightness adjusting method are provided. The method comprises: sensing an environmental light intensity; generating a brightness adjustment signal according to the environmental light intensity via a second control unit; and adjusting a display brightness of a display unit according to the brightness adjustment signal via a first control unit or the second control unit.

Abstract: A data protecting method and a memory storage device are provided. The data protecting method includes reading a first string from the rewritable non-volatile memory module to obtain a data string; performing a decoding operation based on the data string to obtain block information corresponding to a plurality of physical erasing units; inputting the block information to an error checking and correcting (ECC) circuit of the memory storage device to generate a second string; and storing the second string into the rewritable non-volatile memory module.

Abstract: An image sensor is provided. The image sensor includes a microlens array having a plurality of microlenses; and a sensor array having a plurality of photoelectric elements that are arranged into a plurality of macro pixels. Each macro pixel includes a first photoelectric element, a second photoelectric element, a third photoelectric element, and a fourth photoelectric element that receive incident light via a first microlens, a second microlens, a third microlens, and a fourth lens in the plurality of microlenses. The first microlens, the second microlens, the third microlens, and the fourth microlens in each macro pixel have a first initial offset, a second initial offset, a third initial offset, and a fourth initial offset, respectively. The first microlens and the second microlens in each of the plurality of macro pixels further have a first additional offset and a second additional offset, respectively.

Abstract: An image sensor is provided. The image sensor includes a microlens array having a plurality of microlenses; and a sensor array having a plurality of photoelectric elements that are arranged into a plurality of macro pixels. Each macro pixel includes a first photoelectric element, a second photoelectric element, a third photoelectric element, and a fourth photoelectric element that receive incident light via a first microlens, a second microlens, a third microlens, and a fourth lens in the plurality of microlenses. The first microlens, the second microlens, the third microlens, and the fourth microlens in each macro pixel have a first initial offset, a second initial offset, a third initial offset, and a fourth initial offset, respectively. The first microlens and the second microlens in each of the plurality of macro pixels further have a first additional offset and a second additional offset, respectively.