Patents by Inventor Tsung-Yi Huang

Tsung-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor composite film with heterojunction and manufacturing method thereof
    Patent number: 9590049
    Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: March 7, 2017
    Assignee: Richtek Technology Corporation
    Inventors: Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang
  • LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170054019
    Abstract: A lateral double diffused metal oxide semiconductor device, includes: a P-type substrate, an epitaxial layer, a P-type high voltage well, a P-type body region, an N-type well, an isolation oxide region, a drift oxide region, a gate, an N-type contact region, a P-type contact region, a top source, a bottom source, and an N-type drain. The P-type body region is between and connects the P-type high voltage well and the surface of the epitaxial layer. The P-type body region includes a peak concentration region, which is beneath and indirect contact the surface of the epitaxial layer, wherein the peak concentration region has a highest P-type impurity concentration in the P-type body region. The P-type impurity concentration of the P-type body region is higher than a predetermined threshold to suppress a parasitic bipolar transistor such that it does not turn ON.
    Type: Application
    Filed: August 1, 2016
    Publication date: February 23, 2017
    Inventor: Tsung-Yi Huang
  • Complementary metal oxide semiconductor device with dual-well and manufacturing method thereof
    Patent number: 9543303
    Abstract: The present invention discloses a dual-well complementary metal oxide semiconductor (CMOS) device and a manufacturing method thereof. The dual-well CMOS device includes a PMOS device region and an NMOS device region. Each of the PMOS and NMOS device regions includes a dual-well (which includes a P-well and an N-well), and each of the PMOS and NMOS device regions includes P-type and N-type lightly doped diffusions (PLDD and NLDD) regions respectively in different wells in the dual well. A separation region is located between the PMOS device region and the NMOS device region, for separating the PMOS device region and the NMOS device region. The depth of the separation region is not less than the depth of any of the P-wells and the N-wells in the PMOS device region and the NMOS device region.
    Type: Grant
    Filed: April 23, 2016
    Date of Patent: January 10, 2017
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • VERTICAL SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160380093
    Abstract: The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.
    Type: Application
    Filed: September 9, 2016
    Publication date: December 29, 2016
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu
  • Dual-well metal oxide semiconductor (MOS) device and manufacturing method thereof
    Patent number: 9525028
    Abstract: A dual-well metal oxide semiconductor (MOS) device includes: a substrate, an epitaxial layer, a first conductive type well, a first conductive type body region, a second conductive type well, a gate, a first conductive type lightly doped diffusion (LDD) region, a second conductive type lightly doped diffusion (LDD) region, a second conductive type source, and a second conductive type drain. The second conductive type well is connected to the first conductive type well in a lateral direction, and an PN junction is formed between the second conductive type well and the first conductive type well. The MOS device includes LDD regions of opposite conductive types, each located in a corresponding well of a corresponding conductive type, to reduce the channel length.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: December 20, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Lateral double diffused metal oxide semiconductor device and manufacturing method thereof
    Patent number: 9520470
    Abstract: A lateral double diffused metal oxide semiconductor device, includes: a P-type substrate, an epitaxial layer, a P-type high voltage well, a P-type body region, an N-type well, an isolation oxide region, a drift oxide region, a gate, an N-type contact region, a P-type contact region, a top source, a bottom source, and an N-type drain. The P-type body region is between and connects the P-type high voltage well and the surface of the epitaxial layer. The P-type body region includes a peak concentration region, which is beneath and indirect contact the surface of the epitaxial layer, wherein the peak concentration region has a highest P-type impurity concentration in the P-type body region. The P-type impurity concentration of the P-type body region is higher than a predetermined threshold to suppress a parasitic bipolar transistor such that it does not turn ON.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: December 13, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Lateral double diffused metal oxide semiconductor device and manufacturing method thereof
    Patent number: 9484437
    Abstract: The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: November 1, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Ching-Yao Yang, Wen-Yi Liao, Hung-Der Su, Kuo-Cheng Chang
  • Vertical semiconductor device having a non-conductive substrate and a gallium nitride layer
    Patent number: 9466552
    Abstract: The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: October 11, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chien-Wei Chiu, Tsung-Yi Huang
  • Insulated gate bipolar transistor with a lateral gate structure and gallium nitride substrate and manufacturing method thereof
    Patent number: 9362381
    Abstract: The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: June 7, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Fang Huang, Tsung-Yi Huang, Chien-Wei Chiu, Tsung-Yu Yang, Ting-Fu Chang, Tsung-Chieh Hsiao, Ya-Hsien Liu, Po-Chin Peng
  • LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160155820
    Abstract: The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.
    Type: Application
    Filed: February 8, 2016
    Publication date: June 2, 2016
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Ching-Yao Yang, Wen-Yi Liao, Hung-Der Su, Kuo-Cheng Chang
  • High voltage device with additional isolation region under gate and manufacturing method thereof
    Patent number: 9343538
    Abstract: A high voltage device includes: a substrate having a first isolation structure to define a device region; a source and a drain in the device region; a gate on the substrate and between the source and the drain; and a second isolation structure. The second isolation structure includes a first isolation region and a second isolation region. The first isolation region is on the substrate and between the source and the drain, and is partially or totally covered by the gate. The second isolation region is in the substrate and below the gate, and has a depth in the substrate which is deeper than the depth of the first isolation region in the substrate, and the length of the second isolation region in a direction along an imaginary line connecting the source and the drain does not exceed one-third length of the first isolation region.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: May 17, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • INSULATED GATE BIPOLAR TRANSISTOR WITH A LATERAL GATE STRUCTURE AND GALLIUM NITRIDE SUBSTRATE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160111519
    Abstract: The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.
    Type: Application
    Filed: December 16, 2015
    Publication date: April 21, 2016
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Fang Huang, Tsung-Yi Huang, Chien-Wei Chiu, Tsung-Yu Yang, Ting-Fu Chang, Tsung-Chieh Hsiao, Ya-Hsien Liu, Po-Chin Peng
  • SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF
    Publication number: 20160099320
    Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 7, 2016
    Applicant: Richtek Technology Corporation
    Inventors: Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang
  • JUNCTION BARRIER SCHOTTKY DIODE
    Publication number: 20160079443
    Abstract: A JBS diode includes a silicon substrate, a first P doped region, a metal layer, a second P doped region, and a first N doped region. The silicon substrate includes an upper surface. An NBL is provided in the bottom of the silicon substrate. An N well is provided between the upper surface and the NBL. The first P doped region is arranged in the N well, and extending downward from the upper surface. The metal layer covers the upper surface, and located on a side of the first P doped region. The second P doped region is arranged in the N well, extending downward from the upper surface, and located at the other side of the first P doped region. The first N doped region is arranged in the N well, extending downward from the upper surface, and located at the other side of the first P doped region.
    Type: Application
    Filed: October 29, 2014
    Publication date: March 17, 2016
    Inventors: Chung-Yu Hung, Ching-Yao Yang, Tzu-Cheng Kao, Tsung-Yi Huang, Wu-Te Weng
  • Lateral double diffused metal oxide semiconductor device and manufacturing method thereof
    Patent number: 9287394
    Abstract: The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: March 15, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Ching-Yao Yang, Wen-Yi Liao, Hung-Der Su, Kuo-Cheng Chang
  • Transient voltage suppression device and manufacturing method thereof
    Patent number: 9257421
    Abstract: The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device limits a voltage drop between two terminals thereof not to exceed a clamp voltage. The TVS device is formed in a stack substrate including a semiconductor substrate, a P-type first epitaxial layer, and a second epitaxial layer stacked in sequence. In the TVS device, a first PN diode is connected to a Zener diode in series, wherein the series circuit is surrounded by a first shallow trench isolation (STI) region; and a second PN diode is connected in parallel to the series circuit, wherein the second PN diode is surrounded by a second STI region. The first STI region and the second STI region both extend from an upper surface to the second epitaxial layer, but not to the first epitaxial layer.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: February 9, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Kuo-Hsuan Lo, Wu-Te Weng
  • Insulated gate bipolar transistor with a lateral gate structure and gallium nitride substrate
    Patent number: 9252219
    Abstract: The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: February 2, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Fang Huang, Tsung-Yi Huang, Chien-Wei Chiu, Tsung-Yu Yang, Ting-Fu Chang, Tsung-Chieh Hsiao, Ya-Hsien Liu, Po-Chin Peng
  • Semiconductor composite film with heterojunction and manufacturing method thereof
    Patent number: 9245746
    Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: January 26, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang
  • Semiconductor device having weak current channel
    Patent number: 9245945
    Abstract: The invention provides a semiconductor device having a weak current channel. The semiconductor device includes a gate, a source and a drain. There are a plurality of insulation layers and a plurality of first conductive type lightly doped regions alternatingly arranged between the gate and the drain; each of the first conductive type lightly doped regions providing a weak current channel between the source and the drain. When the gate is in a relatively low voltage range, the weak current channel is conducted; when the gate is in a relatively high voltage range, the weak current channel is not conducted.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: January 26, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu, Huang-Ping Chu, Chien-Kai Chang
  • TRANSIENT VOLTAGE SUPPRESSION DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150364460
    Abstract: The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device limits a voltage drop between two terminals thereof not to exceed a clamp voltage. The TVS device is formed in a stack substrate including a semiconductor substrate, a P-type first epitaxial layer, and a second epitaxial layer stacked in sequence. In the TVS device, a first PN diode is connected to a Zener diode in series, wherein the series circuit is surrounded by a first shallow trench isolation (STI) region; and a second PN diode is connected in parallel to the series circuit, wherein the second PN diode is surrounded by a second STI region. The first STI region and the second STI region both extend from an upper surface to the second epitaxial layer, but not to the first epitaxial layer.
    Type: Application
    Filed: June 2, 2015
    Publication date: December 17, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Kuo-Hsuan Lo, Wu-Te Weng