Patents by Inventor Tsung-Yuan (Charlie) Tai
Tsung-Yuan (Charlie) Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10938712Abstract: Apparatus and method to facilitate networked compute node cluster routing are disclosed herein. In some embodiments, a compute node for cluster compute may include one or more input ports to receive data packets from first selected ones of a cluster of compute nodes; one or more output ports to route data packets to second selected ones of the cluster of computer nodes; and one or more processors, wherein the one or more processors includes logic to determine a particular output port, of the one or more output ports, to which a data packet received at the one or more input ports is to be routed, and wherein the logic is to exclude output ports associated with links indicated in fault status information as having a fault status to be the particular output port to which the data packet is to be routed.Type: GrantFiled: February 15, 2017Date of Patent: March 2, 2021Assignee: Intel CorporationInventors: Ken Schumm, Sameh Gobriel, Asif H. Haswarey, Tsung-Yuan Charlie Tai
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Patent number: 10845995Abstract: Examples may include techniques to control an insertion ratio or rate for a cache. Examples include comparing cache miss ratios for different time intervals or windows for a cache to determine whether to adjust a cache insertion ratio that is based on a ratio of cache misses to cache insertions.Type: GrantFiled: June 30, 2017Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Yipeng Wang, Ren Wang, Sameh Gobriel, Tsung-Yuan Charlie Tai
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Patent number: 10394784Abstract: Technologies for managing lookup tables are described. The lookup tables may be used for a two-level lookup scheme for packet processing. When the tables need to be updated with a new key for packet processing, information about the new key may be added to a first-level lookup table and a second-level lookup table. The first-level lookup table may be used to identify a handling node for an obtained packet, and the handling node may perform a second-level table lookup to obtain information for further packet processing. The first lookup table may be replicated on all the nodes in a cluster, and the second-level lookup table may be unique to each node in the cluster. Other embodiments are described herein and claimed.Type: GrantFiled: December 22, 2016Date of Patent: August 27, 2019Assignee: Intel CorporationInventors: Byron Marohn, Christian Maciocco, Sameh Gobriel, Ren Wang, Wei Shen, Tsung-Yuan Charlie Tai, Saikrishna Edupuganti
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Publication number: 20190004709Abstract: Examples may include techniques to control an insertion ratio or rate for a cache. Examples include comparing cache miss ratios for different time intervals or windows for a cache to determine whether to adjust a cache insertion ratio that is based on a ratio of cache misses to cache insertions.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: Yipeng WANG, Ren WANG, Sameh GOBRIEL, Tsung-Yuan Charlie TAI
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Publication number: 20180234336Abstract: Apparatus and method to facilitate networked compute node cluster routing are disclosed herein. In some embodiments, a compute node for cluster compute may include one or more input ports to receive data packets from first selected ones of a cluster of compute nodes; one or more output ports to route data packets to second selected ones of the cluster of computer nodes; and one or more processors, wherein the one or more processors includes logic to determine a particular output port, of the one or more output ports, to which a data packet received at the one or more input ports is to be routed, and wherein the logic is to exclude output ports associated with links indicated in fault status information as having a fault status to be the particular output port to which the data packet is to be routed.Type: ApplicationFiled: February 15, 2017Publication date: August 16, 2018Inventors: Ken Schumm, Sameh Gobriel, Asif H. Haswarey, Tsung-Yuan Charlie Tai
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Publication number: 20180181604Abstract: Technologies for managing lookup tables are described. The lookup tables may be used for a two-level lookup scheme for packet processing. When the tables need to be updated with a new key for packet processing, information about the new key may be added to a first-level lookup table and a second-level lookup table. The first-level lookup table may be used to identify a handling node for an obtained packet, and the handling node may perform a second-level table lookup to obtain information for further packet processing. The first lookup table may be replicated on all the nodes in a cluster, and the second-level lookup table may be unique to each node in the cluster. Other embodiments are described herein and claimed.Type: ApplicationFiled: December 22, 2016Publication date: June 28, 2018Inventors: BYRON MAROHN, CHRISTIAN MACIOCCO, SAMEH GOBRIEL, REN WANG, WEI SHEN, TSUNG-YUAN CHARLIE TAI, SAIKRISHNA EDUPUGANTI
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Patent number: 9256268Abstract: Methods and apparatus for implementing active interconnect link power management using an adaptive low-power link-state entry policy. The power state of an interconnect link or fabric is changed in response to applicable conditions determined by low-power link-state entry policy logic in view of runtime traffic on the interconnect link or fabric. The low-power link-state policy logic may be configured to include consideration of operating system input and Quality of Service (QoS) requirements for applications and devices employing the link or fabric, and device latency tolerance requirements.Type: GrantFiled: April 24, 2012Date of Patent: February 9, 2016Assignee: Intel CorporationInventors: Ren Wang, Ahmad Samih, Christian Maciocco, Tsung-Yuan Charlie Tai, James Jimbo Alexander, Prashant R. Chandra
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Patent number: 9183144Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.Type: GrantFiled: December 14, 2012Date of Patent: November 10, 2015Assignee: Intel CorporationInventors: Ren Wang, Ahmad Samih, Eric Delano, Pinkesh J. Shah, Zeshan A. Chishti, Christian Maciocco, Tsung-Yuan Charlie Tai
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Patent number: 9176875Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.Type: GrantFiled: March 5, 2013Date of Patent: November 3, 2015Assignee: Intel CorporationInventors: Ren Wang, Ahmad Samih, Eric Delano, Pinkesh J. Shah, Zeshan A. Chishti, Christian Maciocco, Tsung-Yuan Charlie Tai
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Patent number: 8892928Abstract: A system and method for maintaining connectivity between a host system running an Always-On-Always-Connected (AOAC) application and an associated remote application server. The system further includes circuitry configured to establish a communication link between the host system and the remote application server. The circuitry is configured periodically transmit keep-alive messages to the remote application server after the host system transitions to and remains in a low-power state. The keep-alive messages are configured to maintain connectivity and presence of the AOAC application with the remote application server while the host system is in the low-power state.Type: GrantFiled: February 28, 2013Date of Patent: November 18, 2014Assignee: Intel CorporationInventors: Christian Maciocco, Sameh Gobriel, Kristoffer Fleming, Gideon Prat, Tsung-Yuan Charlie Tai
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Publication number: 20140195833Abstract: Methods and apparatus for implementing active interconnect link power management using an adaptive low-power link-state entry policy. The power state of an interconnect link or fabric is changed in response to applicable conditions determined by low-power link-state entry policy logic in view of runtime traffic on the interconnect link or fabric. The low-power link-state policy logic may be configured to include consideration of operating system input and Quality of Service (QoS) requirements for applications and devices employing the link or fabric, and device latency tolerance requirements.Type: ApplicationFiled: April 24, 2012Publication date: July 10, 2014Inventors: Ren Wang, Ahmad Samih, Christian Maciocco, Tsung-Yuan Charlie Tai, James Jimbo Alexander, Prashant R. Chandra
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Publication number: 20140173207Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Inventors: Ren Wang, Ahmad Samih, Eric Delano, Pinkesh J. Shah, Zeshan A. Chishti, Christian Maciocco, Tsung-Yuan Charlie Tai
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Publication number: 20140173206Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.Type: ApplicationFiled: March 5, 2013Publication date: June 19, 2014Inventors: Ren Wang, Ahmad Samih, Eric Delano, Pinkesh J. Shah, Zeshan A. Chishti, Christian Maciocco, Tsung-Yuan Charlie Tai
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Patent number: 8566625Abstract: A system and method for maintaining connectivity between a host system running an Always-On-Always-Connected (AOAC) application and an associated remote application server includes determining a timing interval Ti for sending keep-alive messages. The timing interval Ti may be determined by selecting a value for a timeout (Ti) to a value between a maximum timeout (Tmax) and a minimum timeout (Tmin), transmitting a keep-alive message, at an interval based on Ti, across a network connection between a client platform running an Always-On-Always-Connected (AOAC) application and a remote application server associated with the AOAC application, checking a status of the network connection, increasing the value for Tmin if the network connection is still active and decreasing the value for Tmax if the network connection has been dropped.Type: GrantFiled: July 1, 2011Date of Patent: October 22, 2013Assignee: Intel CorporationInventors: Sameh Gobriel, Christian Maciocco, Kristoffer Fleming, Gideon Prat, Tsung-Yuan Charlie Tai
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Publication number: 20130198547Abstract: A system and method for maintaining connectivity between a host system running an Always-On-Always-Connected (AOAC) application and an associated remote application server. The system further includes circuitry configured to establish a communication link between the host system and the remote application server. The circuitry is configured periodically transmit keep-alive messages to the remote application server after the host system transitions to and remains in a low-power state. The keep-alive messages are configured to maintain connectivity and presence of the AOAC application with the remote application server while the host system is in the low-power state.Type: ApplicationFiled: February 28, 2013Publication date: August 1, 2013Inventors: Christian Maciocco, Sameh Gobriel, Kristoffer Fleming, Gideon Prat, Tsung-Yuan Charlie Tai
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Patent number: 8488484Abstract: A power saving method, system and apparatus may include detecting a traffic mode based on statistics of packet network traffic. A packet-free time may be predicted based on a quality of service metric associated with the traffic mode. A low power state may be entered based on the predicted packet-free time, the quality of service metric and the traffic mode. Other embodiments are described and claimed.Type: GrantFiled: September 23, 2010Date of Patent: July 16, 2013Assignee: Intel CorporationInventors: Sameh Gobriel, Jr-Shian Tsai, Tsung-Yuan Charlie Tai
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Patent number: 8483093Abstract: Includes a method that determines utilization of a link and determines a weight for the link based on an energy metric for the determined utilization. The method also includes transmitting the determined weight to at least one node adjacent in the network to the network forwarding device, and determining forwarding based on the transmitted weight.Type: GrantFiled: June 30, 2009Date of Patent: July 9, 2013Assignee: Intel CorporationInventors: Ren Wang, Tsung-Yuan Charlie Tai, Jr-Shian James Tsai, Sameh Gobriel, Jong Han Park
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Patent number: 8402289Abstract: A system and method for maintaining connectivity between a host system running an Always-On-Always-Connected (AOAC) application and an associated remote application server. The system further includes circuitry configured to establish a communication link between the host system and the remote application server. The circuitry is configured periodically transmit keep-alive messages to the remote application server after the host system transitions to and remains in a low-power state. The keep-alive messages are configured to maintain connectivity and presence of the AOAC application with the remote application server while the host system is in the low-power state.Type: GrantFiled: December 30, 2011Date of Patent: March 19, 2013Assignee: Intel CorporationInventors: Christian Maciocco, Sameh Gobriel, Kristoffer Fleming, Gideon Prat, Tsung-Yuan Charlie Tai
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Publication number: 20130007484Abstract: A system and method for maintaining connectivity between a host system running an Always-On-Always-Connected (AOAC) application and an associated remote application server includes determining a timing interval Ti for sending keep-alive messages. The timing interval Ti may be determined by selecting a value for a timeout (Ti) to a value between a maximum timeout (Tmax) and a minimum timeout (Tmin), transmitting a keep-alive message, at an interval based on Ti, across a network connection between a client platform running an Always-On-Always-Connected (AOAC) application and a remote application server associated with the AOAC application, checking a status of the network connection, increasing the value for Tmin if the network connection is still active and decreasing the value for Tmax if the network connection has been dropped.Type: ApplicationFiled: July 1, 2011Publication date: January 3, 2013Inventors: Sameh Gobriel, Christian Maciocco, Kristoffer Fleming, Gideon Prat, Tsung-Yuan Charlie Tai
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Publication number: 20130007495Abstract: A system and method for maintaining connectivity between a host system running an Always-On-Always-Connected (AOAC) application and an associated remote application server. The system further includes circuitry configured to establish a communication link between the host system and the remote application server. The circuitry is configured periodically transmit keep-alive messages to the remote application server after the host system transitions to and remains in a low-power state. The keep-alive messages are configured to maintain connectivity and presence of the AOAC application with the remote application server while the host system is in the low-power state.Type: ApplicationFiled: December 30, 2011Publication date: January 3, 2013Inventors: Christian Maciocco, Sameh Gobriel, Kristoffer Fleming, Gideon Prat, Tsung-Yuan Charlie Tai