Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: A receiver for reducing a system start-up time includes an antenna, an RF (Radio Frequency) circuit, a demodulation circuit, and a data slicer. The data slicer includes a filter, a comparator, a switch, and a delay generator. The filter filters a demodulated signal so as to generate a threshold level. The comparator has a positive input terminal for receiving the demodulated signal and a negative input terminal for receiving the threshold level. The comparator compares the demodulated signal with the threshold level so as to generate a digital signal. The switch is coupled between the positive input terminal and the negative input terminal. The delay generator determines whether or not to close the switch during a delay time according to an enable signal.

Abstract: A DC-DC conversion device is provided. The DC-DC conversion device includes a control signal generator, a conversion module and a comparison module. The control signal generator generates a control signal according to a delay signal. The conversion module is coupled to the control signal generator to convert an input voltage to an output voltage according to the control signal. The comparison module is coupled to the control signal generator and conversion module to compare the output voltage with a reference voltage and output the delay signal according to the comparison result, an enable signal and a clock signal.

Abstract: The invention provides a low noise amplifier. The low noise amplifier includes a first transistor, a second transistor, and a first resistor. The first transistor has a gate to receiving a radio frequency input signal, wherein the source of the first transistor is coupled to a ground voltage. The second transistor has a drain to output a radio frequency output signal, wherein the gate of the second transistor is coupled to a first reference voltage. The first resistor is coupled between the drain of the first transistor and the source of the second transistor.

Abstract: A DC-DC conversion device is provided. The DC-DC conversion device includes a control signal generator, a conversion module and a comparison module. The control signal generator generates a control signal according to a delay signal. The conversion module is coupled to the control signal generator to convert an input voltage to an output voltage according to the control signal. The comparison module is coupled to the control signal generator and conversion module to compare the output voltage with a reference voltage and output the delay signal according to the comparison result, an enable signal and a clock signal.

Abstract: A method for forming uniform, sharply defined periodic regions of reversed polarization within a unidirectionally polarized ferroelectric material proceeds as a two-step process. First, alignment keys are formed on upper and lower planar surfaces of a unidirectionally polarized ferroelectric material by producing a spaced pair of alignment key shaped domain reversed regions and etching alignment key shaped notches in the upper and lower surfaces where the domain reversed regions intersect the surface planes. These notches, being vertically aligned between the upper and lower surfaces, are then used to align photomasks over a surface coating of photoresist formed directly on the material surface or on SiO2 layers coating the material surface.

Abstract: A method of patterning and fabricating poled dielectric microstructures in dielectric materials comprising the following steps. A poled dielectric microstructure within a dielectric material is provided. The poled dielectric microstructure is then segmented into a plurality of independent sub-structures. The poled dielectric microstructures are then fabricated within each of the plurality of independent sub-structures. Additional processes and a novel poling setup for improving and implementing this patterning and fabrication method are also disclosed.

Abstract: A method of patterning and fabricating poled dielectric microstructures in dielectric materials comprising the following steps. A poled dielectric microstructure within a dielectric material is provided. The poled dielectric microstructure is then segmented into a plurality of independent sub-structures. The poled dielectric microstructures are then fabricated within each of the plurality of independent sub-structures. Additional processes and a novel poling setup for improving and implementing this patterning and fabrication method are also disclosed.