Abstract: A surface mount structure comprises a redistribution structure, an electrical connection and an encapsulant. The redistribution structure has a first surface and a second surface opposite the first surface. The electrical connection is on the first surface of the redistribution structure. The encapsulant encapsulates the first surface of the redistribution structure and the electrical connection. A portion of the electrical connection is exposed by the encapsulant.

Abstract: An optical device includes a carrier including a light transmitting layer and a light shielding layer disposed on the light transmitting layer. The optical device further includes a light emitter disposed on the carrier and a light detector disposed on the carrier. The optical device further includes a light transmitting encapsulant encapsulating the light emitter and the light detector, and a light shielding wall disposed in the light transmitting encapsulant and in contact with the light transmitting encapsulant and the light shielding layer.

Abstract: A surface mount structure includes a substrate, a sensor, an electrical contact and a package body. The substrate has a first surface and a second surface opposite to the first surface. The sensor is disposed adjacent to the second surface of the substrate. The electrical contact is disposed on the first surface of the substrate. The package body covers the first surface and the second surface of the substrate, a portion of the sensor and a first portion of the electrical contact.

Abstract: An optical device includes a carrier including a light transmitting layer and a light shielding layer disposed on the light transmitting layer. The optical device further includes a light emitter disposed on the carrier and a light detector disposed on the carrier. The optical device further includes a light transmitting encapsulant encapsulating the light emitter and the light detector, and a light shielding wall disposed in the light transmitting encapsulant and in contact with the light transmitting encapsulant and the light shielding layer.

Abstract: A surface mount structure comprises a redistribution structure, an electrical connection and an encapsulant. The redistribution structure has a first surface and a second surface opposite the first surface. The electrical connection is on the first surface of the redistribution structure. The encapsulant encapsulates the first surface of the redistribution structure and the electrical connection. A portion of the electrical connection is exposed by the encapsulant.

Abstract: A light emitting package includes a metal plate, a plurality of LED chips, a plurality of leads and a molding compound. The metal plate has a first surface and a second surface, and is bent into two chip mounting portions, wherein an inclination angle is between the chip mounting portions. The LED chips are mounted on the first surface and the second surface of the chip mounting portions. The leads are disposed adjacent to the metal plate and electrically connected to the LED chips. The molding compound encapsulates the LED chips and a part of the lead.

Abstract: A light emitting package includes a metal plate, a plurality of LED chips, a plurality of leads and a molding compound. The metal plate has a first surface and a second surface, and is bent into two chip mounting portions, wherein an inclination angle is between the chip mounting portions. The LED chips are mounted on the first surface and the second surface of the chip mounting portions. The leads are disposed adjacent to the metal plate and electrically connected to the LED chips. The molding compound encapsulates the LED chips and a part of the lead.

Abstract: A semiconductor package includes a semiconductor structure. The semiconductor structure includes a plurality of dielectric layers and a plurality of conductive interconnects embedded in the semiconductor structure. The semiconductor structure also includes a plurality of proximity communication signal input terminals. At least one of the plurality of proximity communication signal input terminals includes a first electrode and a second electrode. The first electrode and the second electrode are spaced apart so as to be configured to provide proximity communication through capacitive coupling. The first electrode is exposed proximate to a surface of the semiconductor structure.

Abstract: A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.

Abstract: The present invention relates to a semiconductor package having at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface upon which the first metal bumps are disposed and a plurality of first signal coupling pads disposed adjacent to the first active surface. The second layer chip is electrically connected to the first layer chip, and includes a second active surface that faces the first active surface and a plurality of second signal coupling pads. The second signal coupling pads are capacitively coupled to the first signal coupling pads so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps, and the second layer chip, and the first metal bumps are partially exposed.

Abstract: A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are disposed on and electrically connected to the first surface and around the cavity. The active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure. The bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.

Abstract: The present invention relates to an apparatus and a method for testing non-contact pads of a semiconductor device to be tested. The apparatus includes an insulating body, at least one testing module and a plurality of probes. The insulating body includes an accommodating cavity, a lower opening and at least one side opening. The side opening communicates with the accommodating cavity and the lower opening. The testing module is disposed in the side opening, and each testing module includes a circuit board and an active chip. The active chip is disposed on and electrically connected to the circuit board. The active chip has a plurality of testing pads exposed to the accommodating cavity. The probes are disposed in the lower opening.

Abstract: A first substrate has a first surface facing a second surface of the second substrate. The active chips are disposed on and electrically connected to the first surface, and spaced apart from each other by an interval, wherein the active chips respectively have a first active surface. The bridge chip is mechanically and electrically connected to the second surface, and has a second active surface partially overlapped with the first active surfaces of the active chips, such that the bridge chip is used for providing a proximity communication between the active chips. The connection structure is disposed between the first surface and the second surface for combining the first substrate and the second substrate.

Abstract: A semiconductor device package and a method of fabricating the same are provided. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively.

Abstract: A semiconductor package includes a semiconductor structure. The semiconductor structure includes a plurality of dielectric layers and a plurality of conductive interconnects embedded in the semiconductor structure. The semiconductor structure also includes a plurality of proximity communication signal input terminals. At least one of the plurality of proximity communication signal input terminals includes a first electrode and a second electrode. The first electrode and the second electrode are spaced apart so as to be configured to provide proximity communication through capacitive coupling. The first electrode is exposed proximate to a surface of the semiconductor structure.

Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, at least one first chip, a dielectric layer and at least one second chip. The first chip is attached and electrically connected to the substrate. The first chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The dielectric layer is disposed on the first active surface. The second chip is attached and electrically connected to the substrate by metal bumps. The second chip includes a second active surface and a plurality of second signal coupling pads. The second active surface contacts the dielectric layer. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The first metal bumps are disposed on the first active surface of the first layer chip. The second layer chip is electrically connected to the first layer chip, and includes a second active surface and a plurality of second signal coupling pads. The second active surface faces the first active surface of the first layer chip. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first layer chip, so as to provide proximity communication between the first layer chip and the second layer chip.

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.

Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.