Abstract: A drive control signal is effectively obtained. An offset control circuit (32) adds an offset to a rotational state signal.

Abstract: A cognitive capacity measuring device utilizes an image display unit for displaying different kinds of images that have been degraded from an original photographic object. A subject can provide an input when he/she discerns the photographic object in the degraded image. Recognition time periods are recorded and matched with predetermined challenge level data parameters to calculate a cognitive capacity of the subject. A statistically significant number of test subjects provide recognition times relative to a specific degraded image so that a normal distribution from a frequency distribution of the number of subjects in relationship to a logarithm of the recognition times can be determined. The normal distribution along with the challenge level parameters can provide an indication of the subject's cognitive capabilities.

Abstract: A technique for achieving a risk-free keyless entry system for vehicles at low costs is disclosed. The keyless entry system includes a transmitter responsive to an operation of an operation unit for transmitting a signal indicative of to-be-sent information toward an on-board device at a prespecified communication rate. The on-board device is attached to inside of a vehicle, for receiving electrical waves as sent from the transmitter and for outputting a control signal used to drive electric motors of door lock actuators and/or a motor of slide door actuator. By changing the communication rate of the signal being sent from the transmitter, the door lock control signal is made shorter in arrival distance than the slide door control signal.

Abstract: In performing a display in accordance with a video signal, a display signal for inspection is supplied to a pixel within a predetermined inspected row to operate an EL element therein and to thereby detect a current that flows through the EL element. The current detection data is stored in a volatile primary memory. In accordance with data obtained in this manner, a variation correcting section sequentially corrects data signals to be supplied to the respective pixel. At the time of turning on power, the variation correcting section performs the correction using the current detection data saved in a secondary memory. With this arrangement, it is possible to execute display variation correction from immediately after turning on power, and it is also possible to execute real-time correction.

Abstract: An integrated driving apparatus having an elongated shape mounted at a peripheral portion of a display apparatus comprising a display section on a panel substrate comprises a logic section, a power supply circuit section, and a D/A converter. The logic section comprises a digital display data processor and a timing signal generator which generates a timing control signal necessary for the display apparatus and the D/A converter converts digital display data obtained by the digital display data processor into analog data. The power supply circuit section generates a power supply voltage used in the display apparatus using a signal from the timing signal generator. The power supply circuit section and the D/A converter are provided on left and right of the logic section with the logic section therebetween so that the power supply circuit section and the D/A converter are placed adjacent to the logic section along a long side direction of the elongated shape of the integrated driving apparatus.

Abstract: A serial-parallel conversion circuit in which power consumption is reduced is provided by using a latch clock generation circuit including multiple latch signal generation circuits which outputs a latch signal with a period of an integer multiple of that of a system clock signal. Here, the latch signal generation circuit includes a gate circuit which receives a control signal and a feedback signal, and outputs, according to a combination of the received control signal and feedback signal, a latch signal obtained by inverting a pulse corresponding to one clock of the system clock signal, and an output synchronization circuit which holds the latch signal output from the gate circuit and at the same time outputs the latch signal as a control signal supplied to a gate circuit of a latch signal generation circuit of the succeeding stage and a feedback signal supplied to the gate circuit of the self stage.

Abstract: A method for mapping higher brain function comprises an fMRI mapping step Si to map a brain function of the subject TP by fMRI, a head portion structural image acquisition step S3 to acquire a head portion structural image IMGs by an MRI system in a state that a headgear HC having a marker is mounted on the head portion of the subject TP, a three-dimensional image combining step S4 to create a three-dimensionally combined image IMGfs by combining the head portion structural image IMGs and the brain functional image IMGf obtained by the fMRI mapping step S1, an optical probe mounting step S5 to specify positions on the headgear HC where optical probes PR1, PR2 are mounted based on the three-dimensionally combined image IMGfs and to mount the optical probes PR1, PR2 at the specified positions and an NIRS measuring step S6 to conduct the NIRS by a NIRS method in a state that the headgear HC loaded with the optical probes PR1, PR2 is mounted on the head portion of the subject TP.

Abstract: A method for mapping higher brain function comprises an fMRI mapping step S1 to map a brain function of the subject TP by fMRI, a head portion structural image acquisition step S3 to acquire a head portion structural image IMGs by an MRI system in a state that a headgear HC having a marker is mounted on the head portion of the subject TP, a three-dimensional image combining step S4 to create a three-dimensionally combined image IMGfs by combining the head portion structural image IMGs and the brain functional image IMGf obtained by the fMRI mapping step S1, an optical probe mounting step S5 to specify positions on the headgear HC where optical probes PR1, PR2 are mounted based on the three-dimensionally combined image IMGfs and to mount the optical probes PR1, PR2 at the specified positions and an NIRS measuring step S6 to conduct the NIRS by a NIRS method in a state that the headgear HC loaded with the optical probes PR1, PR2 is mounted on the head portion of the subject TP.

Abstract: The present invention provides a crusher that is capable of crushing material such as waste rubber material under the conditions of room temperature without causing heating due to excessive friction, etc. The crusher of the invention comprises a pair of crushing panels, each crushing panel having crushing blades on the face opposing the other crushing panel; a charging port for charging material to be crushed into a space where the crushing panels oppose each other, the charging port being formed near the center of one of the crushing panels; and a driving part for rotating at least one of the crushing panels; wherein the angle formed by the pair of the crushing panels is smaller on the circumference side of the opposing faces of the crushing panels than on the central side of the opposing faces of the crushing panels.

Abstract: In order to establish a method to measure the cognitive capacity to reconstruct from incomplete data original data explainable by correspondence to brain function, to apply these results to conduct research on brain function and in the future to select and determine the suitability of training appropriate to each individual, and to contribute to early detection, etc.

Abstract: A serial-parallel conversion circuit in which power consumption is reduced is provided by using a latch clock generation circuit including multiple latch signal generation circuits which outputs a latch signal with a period of an integer multiple of that of a system clock signal. Here, the latch signal generation circuit includes a gate circuit which receives a control signal and a feedback signal, and outputs, according to a combination of the received control signal and feedback signal, a latch signal obtained by inverting a pulse corresponding to one clock of the system clock signal, and an output synchronization circuit which holds the latch signal output from the gate circuit and at the same time outputs the latch signal as a control signal supplied to a gate circuit of a latch signal generation circuit of the succeeding stage and a feedback signal supplied to the gate circuit of the self stage.

Abstract: A method for mapping higher brain function comprises an fMRI mapping step S1 to map a brain function of the subject TP by fMRI, a head portion structural image acquisition step S3 to acquire a head portion structural image IMGs by an MRI system in a state that a headgear HC having a marker is mounted on the head portion of the subject TP, a three-dimensional image combining step S4 to create a three-dimensionally combined image IMGfs by combining the head portion structural image IMGs and the brain functional image IMGf obtained by the fMRI mapping step S1, an optical probe mounting step S5 to specify positions on the headgear HC where optical probes PR1, PR2 are mounted based on the three-dimensionally combined image IMGfs and to mount the optical probes PR1, PR2 at the specified positions and an NIRS measuring step S6 to conduct the NIRS by a NIRS method in a state that the headgear HC loaded with the optical probes PR1, PR2 is mounted on the head portion of the subject TP.