Abstract: A radio receiver having a counter which generates a count value corresponding to the frequency of a station to be received which value is stored in a memory through a load enable signal produced when a ramp voltage reaches a value corresponding to a comparison voltage set to correspond to the frequency. The stored count value controls a programmable divider of a phase lock loop circuit to cause the oscillator of the circuit to produce the correct local oscillator frequency to be received. An N-nary counter permits only every Nth count value to be stored in the memory to correspond to the frequency spacing between stations.

Abstract: The reference signal output from a reference oscillator is applied to a counter where the reference signal is counted to provide a count output as a changeable digital value. A saw-tooth wave generator is provided so as to generate a saw-tooth wave such that the saw-tooth wave is changeable of the waveform in synchronism with the count output. A comparison voltage generator is also provided which may typically comprise a variable resistor. A load enable signal generator is provided to receive the saw-tooth wave output from the saw-tooth wave generator and the comparison voltage output as set in the comparison voltage generator. The load enable signal generator is structured to compare the saw-tooth wave output and the comparison voltage output to provide a load enable signal whenever both outputs coincide with each other.

Abstract: A digital frequency synthesizer radio receiver, comprising a scan memory for storing a digital value data concerning a broadcasting frequency; a digital value data entry device for selectively entering a digital value concerning a broadcasting frequency; a preset memory having a plurality of storing locations, each adapted for storing a digital value concerning a specified broadcasting frequency, a channel selector coupled to said preset memory for selecting one of said storing locations thereof, said preset memory being responsive to said channel selector and said digital value data entry device for loading the entered digital value data in the location of the preset memory selected by the channel selector; and a phase locked loop selectively and operatively coupled to either of said scan memory and said preset memory for providing an oscillation frequency signal the frequency of which is associated with the digital value data loaded in the selected one of said scan memory and the preset memory.

Abstract: A variable capacitance semiconductor device is provided wherein a plurality of capacitance elements each having a fixed capacitance value are coupled in parallel with each other and at least two insulated gate field effect transistors are provided for each of the plurality of capacitance elements, whereby the total length of the insulated gate field effect transistors is made as long as possible and accordingly the resistance across the transistors when these are turned on becomes small. Each capacitance element may comprise a single semiconductor substrate of one conductivity type, an opposite conductivity type region formed on one surface of the substrate, an insulating layer formed on the opposite conductivity type region and an electrode formed on the insulating layer. The above described at least two insulated gate field effect transistors are formed such that the above described substrate is shared.

Abstract: A lock detecting circuit of a phase locked loop, comprising a phase comparator for receiving a reference frequency signal and a signal being compared with the reference frequency signal, a charging/discharging circuit which is charge/discharge controlled responsive to the output of the phase comparator and either of the above described two signals, and a delay flip-flop responsive to the output of the charging/discharging circuit and in synchronism with the signal applied to the charging/discharging circuit for assuming one storing state for providing an output representative of the phase difference between the above described two signals.

Abstract: A flip-flop having a reset preferential function, comprising a set input terminal, a reset input terminal, a clock signal source operatively coupled through a field effect transistor to the set input terminal, a capacitance formed at the gate electrode of the field effect transistor, a charge control transistor controllable responsive to the clock signal for precharging the capacitance prior to the clock signal, a discharge control transistor controllable responsive to the reset signal for discharging the capacitance, whereby the capacitance is precharged prior to the clock signal and is discharged responsive to the reset signal, the field effect transistor being rendered conductive as a function of the electric charge of the capacitance, the clock signal source being operatively coupled to the set input terminal as a function of the conduction state of the field effect transistor, whereby the flip-flop is set responsive to the leading edge of the clock signal and is reset responsive to the reset signal in pr