Patents by Inventor Tsutomu Okazaki
Tsutomu Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220266253Abstract: A sample crushing device is provided having a function of stably absorbing vibration of a support member supporting a sample container and vibration of other members which accompanies the vibration. When a rotating shaft 20 is rotated and driven by rotation driving mechanism, revolving motions of a first support member 12 around an axis line C1 of a rotating shaft 20 and rotational movement of an inclined shaft 10 around an axis line C2 arm restrained by a base 1 via first elastic members 14. As a result, the first support member 12 and sample containers 41 are vibrated in plural directions, and samples housed in the sample containers 41 are crushed by crushing media. Vibration of the first support member 12 in plural directions is absorbed by a base 1 via the first elastic members 14 coupled with each of the first support member 12 and the base 1.Type: ApplicationFiled: March 19, 2021Publication date: August 25, 2022Inventors: Tsutomu Okazaki, Atsushi Watanabe, Chuichi Watanabe
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Patent number: 10910394Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: May 22, 2020Date of Patent: February 2, 2021Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Akira Kato, Kan Yasui, Kyoya Nitta, Digh Hisamoto, Yasushi Ishii, Daisuke Okada, Toshihiro Tanaka, Toshikazu Matsui
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Publication number: 20200357807Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: May 22, 2020Publication date: November 12, 2020Inventors: Tsutomu OKAZAKI, Akira KATO, Kan YASUI, Kyoya NITTA, Digh HISAMOTO, Yasushi ISHII, Daisuke OKADA, Toshihiro TANAKA, Toshikazu MATSUI
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Patent number: 10692878Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: August 27, 2019Date of Patent: June 23, 2020Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Akira Kato, Kan Yasui, Kyoya Nitta, Digh Hisamoto, Yasushi Ishii, Daisuke Okada, Toshihiro Tanaka, Toshikazu Matsui
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Publication number: 20190386013Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: August 27, 2019Publication date: December 19, 2019Inventors: Tsutomu OKAZAKI, Akira KATO, Kan YASUI, Kyoya NITTA, Digh HISAMOTO, Yasushi ISHII, Daisuke OKADA, Toshihiro TANAKA, Toshikazu MATSUI
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Patent number: 10424665Abstract: There is improved performance of a semiconductor device including a fin-type low-withstand-voltage transistor and a fin-type high-withstand-voltage transistor. A low-withstand-voltage transistor is formed on each of a plurality of first fins isolated from each other by a first element isolation film, and a high-withstand-voltage transistor, which has a channel region including tops and side surfaces of a plurality of second fins and a top of a semiconductor substrate between the second fins adjacent to each other, is formed. At this time, a top of a second element isolation film surrounding the second fins including part of the channel region of one high-withstand-voltage transistor is lower than a top of the first element isolation film.Type: GrantFiled: August 29, 2017Date of Patent: September 24, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Okamoto, Tsutomu Okazaki
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Patent number: 10396089Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: November 27, 2018Date of Patent: August 27, 2019Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Publication number: 20190096896Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATO, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
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Patent number: 10141324Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: April 28, 2017Date of Patent: November 27, 2018Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Publication number: 20180122930Abstract: There is improved performance of a semiconductor device including a fin-type low-withstand-voltage transistor and a fin-type high-withstand-voltage transistor. A low-withstand-voltage transistor is formed on each of a plurality of first fins isolated from each other by a first element isolation film, and a high-withstand-voltage transistor, which has a channel region including tops and side surfaces of a plurality of second fins and a top of a semiconductor substrate between the second fins adjacent to each other, is formed. At this time, a top of a second element isolation film surrounding the second fins including part of the channel region of one high-withstand-voltage transistor is lower than a top of the first element isolation film.Type: ApplicationFiled: August 29, 2017Publication date: May 3, 2018Inventors: Shinichi OKAMOTO, Tsutomu OKAZAKI
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Publication number: 20170229469Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: April 28, 2017Publication date: August 10, 2017Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATO, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
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Patent number: 9640546Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: January 30, 2015Date of Patent: May 2, 2017Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Patent number: 9136567Abstract: The present invention relates to a chuck mechanism of a charge-discharge test device for a thin secondary battery, and aims to provide a chuck mechanism having excellent action controllability. The chuck mechanism includes: a chuck drive part which is movable in a direction toward a battery container housing a thin secondary battery; and a chuck activation part which is located away from the chuck drive part in the direction toward the battery container and whose movement in the same direction is restricted. In the chuck mechanism, when the chuck unit is moved in the direction toward the battery container, the chuck drive part activates a chuck member of the chuck activation part whose movement in the same direction is restricted.Type: GrantFiled: June 20, 2011Date of Patent: September 15, 2015Assignee: NISSAN MOTOR CO., LTD.Inventors: Takashi Nishihara, Takahiro Kawasaki, Tsutomu Okazaki, Takeshi Yasooka, Yoshikazu Niwa
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Publication number: 20150137215Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: January 30, 2015Publication date: May 21, 2015Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATO, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
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Patent number: 8963226Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: August 20, 2013Date of Patent: February 24, 2015Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Patent number: 8753060Abstract: An article transfer device with a simpler structure is provided which can transfer an article to a proper position. Operation of a first projecting and retracting motor is stopped when torque that is greater than or equal to a first preset value occurs in the first projecting and retracting motor when a first article holder is being projected toward a projected position by operation of the first projecting and retracting motor. And operation of a second projecting and retracting motor is stopped when torque that is greater than or equal to a first preset value occurs in the second projecting and retracting motor when a second article holder is being projected toward a projected position by operation of the second projecting and retracting motor.Type: GrantFiled: February 27, 2013Date of Patent: June 17, 2014Assignee: Daifuku Co., Ltd.Inventors: Yuichi Ueda, Masashige Iwata, Tsutomu Okazaki, Takashi Nishihara, Kazuhiko Kodera
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Publication number: 20140069775Abstract: An article transfer device with a simpler structure is provided which can transfer an article to a proper position. Operation of a first projecting and retracting motor is stopped when torque that is greater than or equal to a first preset value occurs in the first projecting and retracting motor when a first article holder is being projected toward a projected position by operation of the first projecting and retracting motor. And operation of a second projecting and retracting motor is stopped when torque that is greater than or equal to a first preset value occurs in the second projecting and retracting motor when a second article holder is being projected toward a projected position by operation of the second projecting and retracting motor.Type: ApplicationFiled: February 27, 2013Publication date: March 13, 2014Applicant: DAIFUKU CO., LTD.Inventors: Yuichi Ueda, Masashige Iwata, Tsutomu Okazaki, Takashi Nishihara, Kazuhiko Kodera
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Patent number: 8618804Abstract: The present invention relates to a chuck mechanism of a charge/discharge testing device for flat-rechargeable batteries and has a proposition to provide a chuck mechanism that makes it possible to lighten conventionally needed troublesome works, that is, for example, works of storing and fixing a large number of flat-rechargeable batteries in a container, and that is capable of surely chucking the flat-rechargeable batteries (electrodes).Type: GrantFiled: June 16, 2011Date of Patent: December 31, 2013Assignees: Fujitsu Telecom Networks Limited, Nissan Motor Co., Ltd.Inventors: Takashi Nishihara, Takahiro Kawasaki, Tsutomu Okazaki, Takeshi Yasooka, Hiroaki Habe, Yoshikazu Niwa
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Publication number: 20130334592Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: Renesas Electronics CorporationInventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATO, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
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Patent number: 8546867Abstract: A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided. One end of an electricity supply line ESL is arranged over a terminal end TE1 and the other end thereof is arranged over a terminal end TE2, and further, the central portion of the electricity supply line ESL is arranged over a dummy part DMY. That is, the terminal end TE1, the terminal end TE2, and the dummy part DMY have substantially the same height, and therefore, most of the electricity supply line ESL arranged from over the terminal end TE1 to over the terminal end TE2 via the dummy part DMY is formed so as to have the same height.Type: GrantFiled: December 31, 2012Date of Patent: October 1, 2013Assignee: Renesas Electronics CorporationInventors: Hiraku Chakihara, Tsutomu Okazaki