Abstract: Disclosed herein is an analog television broadcast signal receiving apparatus including: a tuner section configured to convert an analog television broadcast signal into a predetermined intermediate frequency band signal; a demodulation circuit section configured to obtain a picture output signal and a sound intermediate frequency signal from the predetermined intermediate frequency band signal coming from the tuner section; a picture processing circuit section configured to convert the picture output signal into a display-ready picture signal; a sound demodulation processing circuit section configured to demodulate the sound intermediate frequency signal; and a control section.

Abstract: Disclosed herein is an analog television broadcast signal receiving apparatus including: a tuner section configured to convert an analog television broadcast signal into a predetermined intermediate frequency band signal; a demodulation circuit section configured to obtain a picture output signal and a sound intermediate frequency signal from the predetermined intermediate frequency band signal coming from the tuner section; a picture processing circuit section configured to convert the picture output signal into a display-ready picture signal; a sound demodulation processing circuit section configured to demodulate the sound intermediate frequency signal; and a control section.

Abstract: A key signal processing apparatus for video signal processing including a signal delay circuit for successively delaying by 1 clock units a key input signal, used for applying a special effect to a video signal, and outputting the delayed key signal; a signal selection circuit for receiving the key input signal and a plurality of delayed key signals output from the signal delay circuit and selecting based on a selection control signal two pairs of signals in predetermined relationships of delay; a first signal interpolation circuit for performing signal interpolation on the first pair output from the signal selection circuit using a first coefficient; a second signal interpolation circuit for performing signal interpolation on the second pair output from the signal selection circuit using a second coefficient; and a signal synthesization circuit for combining a signal from the output of the first signal interpolation circuit and the output of the second signal interpolation circuit and outputting it as a key

Abstract: A digital switcher of this invention comprises a matrix switcher section 11 adapted so that a plurality of serial digital video signals are inputted through respective input buses, a control section 12 for carrying out operation control of the matrix switcher section 11, signal processing sections 13A, 13B . . . connected to a plurality of output buses of the matrix switcher section 11, an input detector 14 connected to one output bus of the matrix switcher section 11, and an error detector 15 connected to one output bus of the matrix switcher section 11. An approach is employed to control the matrix switcher section 11 by the control section 12 with respect to a plurality of digital video signals inputted through respective input buses to thereby selectively detect presence or absence of input and occurrence of error by the input detector 14 and the error detector 15 connected to one output bus of the matrix switcher section 11.

Abstract: A key signal processing apparatus for video signal processing including a signal delay circuit for successively delaying by 1 clock units a key input signal, used for applying a special effect to a video signal, and outputting the delayed key signal; a signal selection circuit for receiving the key input signal and a plurality of delayed key signals output from the signal delay circuit and selecting based on a selection control signal two pairs of signals in predetermined relationships of delay; a first signal interpolation circuit for performing signal interpolation on the first pair output from the signal selection circuit using a first coefficient; a second signal interpolation circuit for performing signal interpolation on the second pair output from the signal selection circuit using a second coefficient; and a signal synthesization circuit for combining a signal from the output of the first signal interpolation circuit and the output of the second signal interpolation circuit and outputting it as a key

Abstract: A key signal processing apparatus for video signal processing including a signal delay circuit for successively delaying by 1 clock units a key input signal, used for applying a special effect to a video signal, and outputting the delayed key signal; a signal selection circuit for receiving the key input signal and a plurality of delayed key signals output from the signal delay circuit and selecting based on a selection control signal two pairs of signals in predetermined relationships of delay; a first signal interpolation circuit for performing signal interpolation on the first pair output from the signal selection circuit using a first coefficient; a second signal interpolation circuit for performing signal interpolation on the second pair output from the signal selection circuit using a second coefficient; and a signal synthesization circuit for combining a signal from the output of the first signal interpolation circuit and the output of the second signal interpolation circuit and outputting it as a key

Abstract: A digital video audio processing apparatus in which serial signal formed digital video signals and digital audio signals, which are supplied to a plurality of input terminals and are multiplexed each other, are converted into parallel signal form respectively; the digital video signals and digital audio signals are separated respectively; switching processing or video special effect processing is performed on a plurality of digital video signals; switching processing or mixing processing is performed on a plurality of digital audio signals; and these processed digital video signals and digital audio signals are multiplexed each other to convert into serial signal form and output them.

Abstract: A digital switcher of this invention comprises a matrix switcher section 11 adapted so that a plurality of serial digital video signals are inputted through respective input buses, a control section 12 for carrying out operation control of the matrix switcher section 11, signal processing sections 13A, 13B . . . connected to a plurality of output buses of the matrix switcher section 11, an input detector 14 connected to one output bus of the matrix switcher section 11, and an error detector 15 connected to one output bus of the matrix switcher section 11. An approach is employed to control the matrix switcher section 11 by the control section 12 with respect to a plurality of digital video signals inputted through respective input buses to thereby selectively detect presence or absence of input and occurrence of error by the input detector 14 and the error detector 15 connected to one output bus of the matrix switcher section 11.

Abstract: A digital video switching apparatus is disclosed in which a 4:2:2 digital video signal and a 4:4:4 digital video signal supplied at input terminals are selected by switching by a matrix switcher unit in order to transmit the 4:2:2 digital video signal to a first signal processing unit and in order to transmit the 4:2:2 digital video signal to a second signal processing unit. The first signal processing unit converts the 4:4:4 digital video signal into the 4:2:2 digital video signal by signal processing, such as color correction. The second signal processing unit performs signal processing, such as mixing or wiping, on the 4:2:2 digital video signal and the 4:2:2 digital video signal directly supplied from the matrix switcher unit, in order to output the processed 4:2:2 digital video signal.

Abstract: An analog-to-digital converter. The VCO 111 generates a sampling clock with a frequency four times that of a subcarrier. The A/D conversion circuit 103 converts an analog composite signal on the basis of the sampling clock thus generated. The BPF 113 extracts an input subcarrier from the digital composite signal. The local subcarrier reference generator 112 generates a local subcarrier. The multiplier 114 detects the phase differences between the input subcarrier and the local subcarrier. The averaging (I) circuit 115 averages consecutive 4 n phase differences. The averaging (II) circuit 116 further averages the averages thus obtained over a plurality of lines. The pulse generator 117 generates a pulse signal with a width corresponding to the averages thus obtained. The integrator 118 integrates the pulse signal thus generated thereby to control the oscillating frequency and phase of the VCO 111.

Abstract: A switcher apparatus for selectively supplying video signals comprising a main switching unit, a back-up switching unit, a switching device and a housing. The main and back-up switching units receive a plurality of input video signals, from which desired video signals are selected and supplied therefrom. The switching device receives the selected video signals from the main and back-up switching units and outputs one of the two received signals. The housing secures the main and back-up switching units and enables removal therefrom and installation therein of one of the main and back-up switching units while the other switching unit operates so as to provide continuous selecting of desired video signals and supplying of the same by at least one of the main and back-up switching units to the switching device.

Abstract: An editing apparatus for editing digital video signals employs a number of video recording and/or reproduction devices, a signal processing mechanism, and a switching mechanism, wherein the number of transfer lines and the area occupied by the associated connectors is decreased by converting parallel signals into serial format.

Abstract: A special effect generating system processes first, second, and third video signals supplied respectively from first, second, and third video signal sources to produce an output video signal with special effects. At a plurality of points of time along a first time base, first control data indicative of positions of edges of a first image represented by the first video signal are generated and stored in a first memory. At a plurality of points of time along a second time base, second control data indicative of positions of a boundary between second and third images represented by the second and third video signals are generated and stored in a second memory. The first, second, and third video signals are combined into the output video signal based on the first and second control data stored in the first and second memories.

Abstract: There is an apparatus for generating a velocity error signal for use in a time base corrector. This apparatus comprises: an A/D converter that converts a velocity error to a digital signal that is fed to a summing circuit to convert it to a phase shift amount. A zero value interpolation circuit multiplies the sampling frequency of the phase shift amount with an integer and a digital low-pass filter interpolates an output signal of the interpolation circuit. A differentiating circuit to convert an interpolated phase shift amount of an output signal of the LPF to a phase difference and a D/A converter 9 converts the digital phase difference data to an analog signal. With this apparatus, the velocity error can be accurately corrected.

Abstract: A write clock generator for a time base corrector incorporated in a video tape recorder can generate a write clock signal including accurate phase and frequency fluctuation information on a reproduced video signal in spite of a simple circuit configuration. A write clock signal is generated from a VCO oscillated in response to a reproduced burst signal, and further the VCO is so controlled on the basis of frequency difference between the oscillated write clock signal and a frequency fluctuation signal such that the frequency difference may be eliminated. The frequency fluctuation signal is generated in response to a horizontal synchronizing signal so as to include time base fluctuations in a reproduced video signal.

Abstract: In a phase error correcting apparatus for correcting the phase of an input sampled signal having discrete digital data at a predetermined sampling period by means of a phase error signal, an interpolating calculation is made therein using digital data of the input sampled signal so that digital data of a corrected output sampled signal at the sampling points can thereby be obtained, and thus, the output sampled signal is obtained in which corrected sampled digital data are produced at the same sampling time points at the predetermined sampling period.

Abstract: A digital chrominance signal processing system for processing an input digital composite chrominance signal, which is sampled with a sampling frequency f.sub.s =2mf.sub.sc, wherein m is an integer and f.sub.sc is a color subcarrier frequency, has a decoder for decoding the input digital composite chrominance signal into digital chrominance components, the decoder including a code converter for inverting the input digital composite chrominance signal and a switch for selectively switching between the input digital composite chrominance signal and an output of the code converter at a switching rate mf.sub.sc.

Abstract: A write clock pulse generator is disclosed, in which a horizontal synchronizing signal is separated from an input video signal and supplied to a PLL (phase locked loop) circuit to form a first clock with the frequency of nf.sub.H (n is an integer), a color burst signal is separated from the input video signal and used to drive a gate type variable oscillator to thereby form a second clock synchronized in phase with the color burst signal and whose average frequency is nf.sub.H, a difference between the pulse widths of the clocks resulting from counting down the first and second clocks to 1/M and the frequency of the variable oscillator is controlled by the compared output therebetween, whereby to produce a second clock synchronized in phase with the color burst signal and the frequency of which is n times the horizontal synchronizing signal.