Patents by Inventor Tsutomu Tashiro

Tsutomu Tashiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5747860
    Abstract: On a surface of a silicon substrate, N.sup.+ type buried layer and N-type epitaxial layer are formed in order, and an isolation layer reaching the silicon substrate from the surface of the N-type epitaxial layer is formed to define a photodiode. In the surface of the photodiode, a rectangular recess is selectively formed toward inside of the N-type epitaxial layer. On the side face of the recess, a silicon oxide layer is formed. In the region surrounded by the silicon oxide layer, a photo absorbing layer and so forth is formed. On the other hand, in an optical waveguide, a LOCOS oxide layer is formed toward inside from the surface of the N-type epitaxial layer. The N-type epitaxial layer is sandwiched between the LOCOS oxide layer and the N.sup.+ type buried layer. The refraction indexes of the LOCOS oxide layer and the N.sup.+ type buried layer are smaller than that of the N-type epitaxial layer.
    Type: Grant
    Filed: March 8, 1996
    Date of Patent: May 5, 1998
    Assignee: Nec Corporation
    Inventors: Mitsuhiro Sugiyama, Tsutomu Tashiro
  • Patent number: 5731622
    Abstract: It is the object of the invention to suppress the leakage current of a semiconductor photodiode. A trench, a side wall of which is covered with and insulating layer, is formed on the surface of a semiconductor substrate of the first conductivity type. Then, an epitaxial layer of the second conductivity type is grown in the trench, where a PN-junction is constructed between the bottom surface of the epitaxial layer and the semiconductor substrate. An impurity diffusion layer of the second conductivity type with higher impurity concentration than that of an internal portion of the epitaxial semiconductor layer is formed over the side surface of the epitaxial layer of the second conductivity type. In the aforementioned structure, when a reverse bias voltage is applied to the PN-junction, a depletion layer does not extend to a neighborhood of the insulating layer, and a leakage current, which flows via surface states near the insulating layer.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: March 24, 1998
    Assignee: NEC Corporation
    Inventors: Mitsuhiro Sugiyama, Tsutomu Tashiro
  • Patent number: 5719768
    Abstract: A lock-up clutch control method controls a torque converter comprising an input shaft through which a rotating force from an engine is input, an output shaft which outputs a driving force to the side of driving wheels and a lock-up clutch which operates in response to a hydraulic pressure. A control element controls an engaging pressure of the lock-up clutch by way of the hydraulic pressure. The engaging force of the clutch is controlled in accordance with calculated results of a target following up section for calculating a controlled variable so that a slip follows up a target slip and a control system stabilizing section for calculating the controlled variable so that the disturbance applied to the control system is compensated. Thereby, a stable control may be realized without receiving any effect of the disturbance. The disturbance may be estimated and learned for more accurate control.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: February 17, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tsutomu Tashiro, Yoshifumi Kato, Tetsuji Kozaki, Masami Fujitsuna
  • Patent number: 5659788
    Abstract: A computer having a terminal unit corresponding to a multiwindow is coupled with a control object system to be operated through communication devices. Furthermore, there are provided in the computer an emulation unit for emulating the operation of a terminal unit operated by respective operating tools software-wise, a unit for aggregating and processing message groups outputted by respective operating tools, a unit for controlling display of aggregated and processed information in a multiwindow, a unit for interpreting and converting the operation from a terminal unit corresponding to a multiwindow into a command group of respective operating tools and a unit for generating a picture interface of a terminal unit corresponding to a multiwindow by interlocking with an existing Office automation (OA) tool, thereby to unify and aggregate functions of a plurality of operating tool groups in one window.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: August 19, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Harushi Someya, Kazuyuki Ikeda, Tsutomu Tashiro, Takatoshi Shimizu
  • Patent number: 5576221
    Abstract: To selectively grow a P type silicon layer and a Si/Ge.sub.x Si.sub.1-x superlattice layer under low temperature conditions in the area encircled with a groove, at least the side walls of which consist of silicon oxide film, which is formed in the silicon substrate. Thereby, the leak at the side of the superlattice layer can be reduced. Furthermore, by burying a metal film in the groove, the loss of light at the side of the superlattice layer can be suppressed to the minimum. Thus a light receiver having silicon/germanium silicon-mixed-crystal layer is stably formed in a silicon semiconductor substrate and optical absorption efficiency can be improved.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: November 19, 1996
    Assignee: NEC Corporation
    Inventors: Hisashi Takemura, Tsutomu Tashiro
  • Patent number: 5508553
    Abstract: A transversal bipolar transistor is structured to have a single crystal semiconductor film provided on a single crystal semiconductor region which is provided on a semiconductor substrate. The semiconductor substrate is of a first conductivity type, and the single crystal semiconductor region is of a second conductivity type which is opposite to the first conductivity type. The single crystal semiconductor film is divided in the transversal direction into a central portion of the second conductivity type for a base region and left and right portions of the first conductivity type for emitter and collector regions. The transversal bipolar transistor may be integrated with a vertical bipolar transistor commonly on the semiconductor substrate.
    Type: Grant
    Filed: November 1, 1994
    Date of Patent: April 16, 1996
    Assignee: NEC Corporation
    Inventors: Satoshi Nakamura, Tsutomu Tashiro
  • Patent number: 5475257
    Abstract: The invention is a semiconductor device having a metal-semiconductor contact structure. The device includes a metal region having such a high conductivity as to serve as a contact plug. The device also includes a first semiconductor region having a first band gap and being so doped with one conductive type dopant as to exhibit a high conductivity. The device also includes a semiconductor film having a second band gap wider than the first band gap. The semiconductor film is in contact at its opposite surfaces with a part of the metal region and a part of the first semiconductor region respectively. The semiconductor film is doped with the one conductive type dopant so heavily as to suppress electrical current flow between the part of the metal region and the part of the first semiconductor region through the semiconductor film. The semiconductor film comprises amorphous silicon or poly-crystalline silicon.
    Type: Grant
    Filed: October 27, 1994
    Date of Patent: December 12, 1995
    Assignee: NEC Corporation
    Inventors: Takasuke Hashimoto, Tsutomu Tashiro
  • Patent number: 5404430
    Abstract: The status or state of a computer system is displayed with respect to at least one subspace having two or more coordinates of display corresponding respectively to different selected status variables of the computer system, which might be utilization factors of respective programs operating in a network. Critical states are defined by critical state formulas, at least one of which involving a plurality of the status variables. The critical state formulas are used to define and display a critical region on the display apparatus with respect to the coordinate system. Values of the status variables, loci of the status variables, indications of change of the status variables, distances of points defined by the status variables from the critical region and the like information are displayed in a subspace with respect to the coordinates to give a visual indication of their relationship to the critical region.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: April 4, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Tashiro, Kazuhiro Takada, Nobuo Kotatsu, Makoto Saitoh, Harushi Someya
  • Patent number: 5323032
    Abstract: A Si-SiGe-Si heterojunction bipolar transistor which has a very thin epitaxial base layer. The device possesses an optimum doping profile across a base layer. The emitter region is higher doping concentration of n.sup.+ -type. The base layer of p-type comprises both a monocrystalline SiGe layer having a lightly doped region on a collector side and a heavily doped region, and a lightly doped monocrystalline Si layer on an emitter side. An emitter side Si-SiGe heterojunction exists in the base layer and a collector side Si-SiGe heterojunction exists in the collector region. Those provides a slope negative gradient of a potential profile from the emitter to collector without a potential barrier for carriers, or electrons or holes. The very thin base layer is connected to an aluminium contact through an external base layer and a base contact layer thereby permitting the very thin base layer to be free from a damage by contacting with a metal such as aluminium.
    Type: Grant
    Filed: September 8, 1992
    Date of Patent: June 21, 1994
    Assignee: NEC Corporation
    Inventors: Fumihiko Sato, Tsutomu Tashiro
  • Patent number: 5321301
    Abstract: The present invention relates to a semiconductor device which comprises: an n.sup.- type buried collector provided on an n type silicon epitaxial layer disposed in an emitter opening; an n.sup.- type silicon collector disposed on said collector; a p.sup.+ type single crystal silicon intrinsic base layer; and an n.sup.+ type single crystal silicon emitter wherein said p.sup.+ type single crystal silicon intrinsic base layer is connected with a p.sup.+ type base electrode polycrystalline silicon through a p.sup.+ type polycrystalline silicon graft base.
    Type: Grant
    Filed: April 7, 1993
    Date of Patent: June 14, 1994
    Assignee: NEC Corporation
    Inventors: Fumihiko Sato, Tsutomu Tashiro
  • Patent number: 5296391
    Abstract: A method of manufacturing a semiconductor device includes a monocrystalline semiconductor layer of one conductivity type with a first insulating film covering the semiconductor layer. An aperture is selectively formed in the first insulating film to expose a part of the semiconductor layer. A first polycrystalline semiconductor film of an opposite conductivity type is formed on the first insulating film and has an overhang portion projecting over the aperture from an edge of the first insulating film defining the aperture.
    Type: Grant
    Filed: May 26, 1993
    Date of Patent: March 22, 1994
    Assignee: NEC Corporation
    Inventors: Fumihiko Sato, Masahiko Nakamae, Mitsuhiro Sugiyama, Tsutomu Tashiro
  • Patent number: 5285088
    Abstract: A semiconductor device capable of reducing element sizes exceedingly and a mask alignment accuracy in lithography is provided. This device has a pair of semiconductor layers for source/drain electrodes formed on the field insulating film so as to be respectively partially projected in a "overhanging-shape" over the active area. For example, using an MBE method, a selectively epitaxial growth is made with these semiconductor layers as nuclei, so that first and second semiconductor layers at the interface of which a channel is formed and a pair of semiconductor layers for source and drain electrode connections can be formed. Accordingly, the semiconductor heterojunction and gate electrode can be formed in self-alignment on the active area with the semiconductor layers pair for source/drain electrodes as the reference, so that a reduction in transistor size can be realized.
    Type: Grant
    Filed: September 16, 1992
    Date of Patent: February 8, 1994
    Assignee: NEC Corporation
    Inventors: Fumihiko Sato, Tsutomu Tashiro
  • Patent number: 5241211
    Abstract: The substrate in a SOI structure is formed of a material with high heat conductivity, a U groove reaches substrate, the buried material inside the U groove is formed of a material with high heat conductivity, and the buried material is brought into contact with the substrate. With this arrangement, the drop in heat radiation effect can be improved while maintaining the enhancement of the resistance to the soft errors and the reduction of the parasitic capacitance on the bottom surface of the semiconductor element, so that the heat radiation effect can be made to approach the heat radiation effect of a semiconductor device having an insulated isolation region of the conventional U-groove structure. Further, in this case the speed and power product can be made better than the speed and power product of a semiconductor device having an insulated isolation region of the conventional U-groove structure.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: August 31, 1993
    Assignee: NEC Corporation
    Inventor: Tsutomu Tashiro
  • Patent number: 5124781
    Abstract: A semiconductor device which includes a semiconductor substrate, an element region formed on one of the principal surfaces of the semiconductor substrate with multilayer wiring structure having an organic film as an interlayer insulating film, a plurality of electrically conductive pillars formed in the periphery of the element region on the principal surface of the substrate, an organic interlayer insulating film formed between the plurality of electrically conductive pillars, and bonding pads formed on the plurality of electrically conductive pillars and extending from the upper layer wiring of the element region.
    Type: Grant
    Filed: March 6, 1990
    Date of Patent: June 23, 1992
    Assignee: NEC Corporation
    Inventor: Tsutomu Tashiro
  • Patent number: 4901229
    Abstract: A plurality of devices for processing IF-THEN JOIN operation of IF-THEN rules are provided to process the JOIN operation in a pipe-line manner. A JOIN operation processing facility has an input buffer for latching status data corresponding to one condition in a certain rule; an associative memory for latching status data corresponding to another condition; an output buffer for latching the result of a JOIN operation; and a data combining arrangement for replacing an item value from the two data by a meaningful value to generate one data so that a series of operations of picking up the data one by one from the input buffer, retrieving associatively the data of the associative memory by using the data picked up as a retrieval data and the common item as a retrieval key, and storing in the output buffer the combined result of the data picked up and the retrieval data.
    Type: Grant
    Filed: January 21, 1986
    Date of Patent: February 13, 1990
    Inventors: Tsutomu Tashiro, Norihisa Komoda, Isao Tsushima, Kuniaki Matsumoto, Kazuhiro Kawashima, Riyoji Maekawa
  • Patent number: 4644480
    Abstract: A reliability analyzing system for manufacturing processes is disclosed, which comprises a computer system provided with a data memory device, a central processing device and input/output devices, terminals which input/output information into/from said computer system, and output devices for manufacturing sites; whereby said data memory device stores required specifications for each product, works for manufacturing and controlling processes, information relating to items, such as required specifications, works, control items, etc. and information mutually relating different items, and on the basis of the stored information, reliability analysis for each process is effected for all the processes and reliability analysis for each required specification is performed for all the required specifications.
    Type: Grant
    Filed: November 16, 1984
    Date of Patent: February 17, 1987
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Koichi Haruna, Kazuo Nakao, Tamotsu Nishiyama, Tsutomu Tashiro, Kuniaki Matsumoto, Nobuyuki Saida
  • Patent number: 4628434
    Abstract: A control system employs a controller for controlling the operation of a plurality of facilities and a memory which stores information employed by the controller for controlling the operation of the facilities. The memory includes a first portion for storing facility status signals and command signals, a second portion which stores a series of rules which are triggered in response to status information from the respective facilities, a portion which converts the rules into internal codes, and a portion which stores the results of the application of the internal codes to control commands. The controller monitors facility status signals and controls the generation of facility status signals. It also controls which rule set number is to be used in accordance with information stored in memory and contains an internal code generator for generating the internal codes corresponding to generated facility status signals.
    Type: Grant
    Filed: May 8, 1984
    Date of Patent: December 9, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Tashiro, Koichi Haruna, Norihisa Komoda
  • Patent number: 4628435
    Abstract: A multi-facility control system includes a controller and attendant memory. Stored in the memory are a plurality of rules, each of which includes a conditional portion representative of a condition to be examined and a conclusive portion describing action to be taken when the condition is satisfied. Also stored in memory is the current status of each facility, information representative of the tasks to be performed by the facilities and updated status information resulting from the satisfaction of the conditional parts of the rules. The controller monitors the status of the facilities and compares monitored status information with the conditional parts of the rules stored in memory. When rule conditions are satisfied, control instructions are generated which are employed to produce command signals that are coupled to the respective facilities for controlling the operations thereof.
    Type: Grant
    Filed: February 9, 1984
    Date of Patent: December 9, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Tashiro, Koichi Haruna, Norihis Komoda