Abstract: A semiconductor device connected to at least one semiconductor device of the same type. The semiconductor device includes first pins, provided on a first side of the semiconductor device, for receiving signals commonly used with the at least one semiconductor device, and second pins, provided on a second side of the semiconductor device substantially perpendicular to the first side, for being connected to signal lines which are not connected to the at least one semiconductor device.

Abstract: An object of the present invention is to provide a multi-cylinder rotary compressor which can eliminate a number of balancers for preventing vibrations. Assuming that the mass eccentricity in a cylinder is m1×r1; the mass eccentricity in another cylinder is m2×r2; the mass eccentricity of a balancer attached to the lower side of a rotator is m3×r3; the mass eccentricity of another balancer attached to the upper side of the rotator is m4×r4; respective distances from the cylinder to another cylinder, the lower balancer and another balancer are L2, L3 and L4, when the balancing is attained with the expressions m1×r1+m4×r4=m2×r2+m3×r3, m4×r4×L4=m2×r2×L2+m3×r3×L3, and m1×r1=m2×r2, the lower balancer is eliminated and the mass eccentricity of the balancer is set to be not less than 20% and not more than 80% of m4×r4.

Abstract: A circuit includes a first phase-adjustment circuit adjusting phases of rising edges and falling edges of an original signal, and a phase-delay circuit receiving a phase-adjusted signal from said first phase-adjustment circuit and generating a delay signal by delaying said phase-adjusted signal by a predetermined phase amount. The circuit further includes a phase-comparison circuit comparing phases of edges between said phase-adjusted signal and said delay signal so as to control said first phase-adjustment circuit such that said phases of edges satisfy a predetermined phase relation.

Abstract: A signal-transfer system for transferring a signal via a line having no anti-signal-reflection resistor. The signal-transfer system includes a line having an equalized characteristic impedance Z.sub.0, and an output circuit having an output turn-on resistance Z.sub.0 /2 and outputting to the line a signal which has a voltage difference between a high level and a low level smaller than about 1 V.

Abstract: A data transmission method exchanges data between at least first and second electronic devices which are coupled via a plurality of bus lines, where each of the bus lines is terminated via a terminating resistor having one end coupled to a bus line and another end applied with a terminating voltage. The data transmission method includes the steps of (a) setting a high logic level of data to a voltage higher than the terminating voltage and setting a low logic level of the data to a voltage lower than the terminating voltage, and (b) continuously outputting the data from the first electronic device to at least one bus line at a timing determined by a first clock signal by alternately repeating a state where the data is output to the one bus line and a state where an impedance between the first electronic device and the one bus line is set to a high impedance.

Abstract: A semiconductor memory device includes a plurality of bit lines, first sense amplifiers each connected to a corresponding one of the plurality of bit lines, and a first data bus laid out in parallel to the plurality of bit lines and connected to the plurality of bit lines via gates and the first sense amplifiers. The semiconductor memory device further includes column-selection lines laid out perpendicularly to the plurality of bit lines to open at least one of the gates to connect the first data bus to the plurality of bit lines.

Abstract: An outline of an SRAM cell is rectangular. The SRAM cell have nMOS transistors QN1 and QN3 in a nMOS region 13A being on one side of the longitudinal direction, nMOS transistors QN2 and QN4 in a nMOS region 13B being on the opposite side thereof, pMOS transistors QP1 and QP2 in a central region 12, and isolation regions 14A and 14B being between the regions 13A and 12 and between the regions 13B and 12 respectively. The pMOS transistors QP1 and QP2 are on the nMOS transistor QN1 side and on the nMOS transistor QN2 side respectively within the region 12. The direction of bit lines is perpendicular to the longitudinal direction and the word line is parallel to the longitudinal direction. The nMOS transistors QN1, QN4 and the pMOS transistor QP1 are placed on one side of the regions 13A, 13B and 12 respectively in the direction perpendicular to the longitudinal direction, whereas the nMOS transistors QN3 and QN2 and the pMOS transistor QP2 are placed on the opposite side thereof.

Abstract: An electronic system includes a plurality of electronic circuits each having a signal input and output function, a bus to which the plurality of electronic circuits are connected, first termination resistors connected to ends of the bus, and a termination voltage circuit having a first part generating a first voltage and a second part generating a second voltage. The sum of the first voltage and the second voltage is supplied, as a power supply voltage, to output circuits of the plurality of electronic circuits connected to the bus. The second voltage is supplied to the first termination resistors as a termination voltage.