Patents by Inventor Tsuyoshi Kaneda

Tsuyoshi Kaneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959702
    Abstract: An air separation device can include: a first compressor and a second compressor for compressing feed air; a first refrigerator and a second refrigerator for cooling the feed air; a pre-purification unit for pre-purifying the feed air; a flow rate measuring unit for measuring the flow rate of the feed air; a main heat exchanger for subjecting the feed air to heat exchange; a purification portion into which the feed air led out from the main heat exchanger is fed, and which separates and purifies product nitrogen and/or product oxygen from the feed air; and a compressor control unit for controlling the feed quantity of the feed air in accordance with an increase or decrease in the production quantity of product nitrogen and/or product oxygen.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: April 16, 2024
    Assignee: L'Air Liquide, Societe Anonyme Pour L'Etude Et L'Exploitation Des Procedes Georges Claude
    Inventors: Takuya Kaneda, Tsuyoshi Sugitani
  • Publication number: 20090014855
    Abstract: A semiconductor integrated circuit device includes a die pad and a semiconductor chip mounted over the die pad, having a main surface with surface electrodes and a back surface. Suspension leads support the die pad, and leads are arranged around the semiconductor chip, each of the leads having inner and outer lead portions. A first plating layer is formed at a part of the inner lead portions and a second plating layer is formed over the outer lead portion. Wires electrically connect the surface electrodes with the inner lead portions through the first plating layer. A resin body seals the die pad, the chip, the wires and the inner lead portions. The second plating layer is comprised of different materials than the first plating layer, and is a Pb-free metal layer.
    Type: Application
    Filed: June 4, 2008
    Publication date: January 15, 2009
    Inventors: Yoshinori MIYAKI, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Patent number: 7397114
    Abstract: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 ?m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Patent number: 7176056
    Abstract: Arrangements are provided to effectively prevent wire disconnection generated due to an increase of heat applied to a semiconductor integrated circuit device The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 ?m is provided in the connecting member.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: February 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Publication number: 20060138617
    Abstract: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 ?m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.
    Type: Application
    Filed: February 28, 2006
    Publication date: June 29, 2006
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Patent number: 7038306
    Abstract: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 ?m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: May 2, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Patent number: 6891253
    Abstract: Arrangements are provided to effectively prevent wire disconnection generated due to an increase of heat applied to a semiconductor integrated circuit device. The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 ?m is provided in the connecting member.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: May 10, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Publication number: 20040245607
    Abstract: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 &mgr;m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.
    Type: Application
    Filed: July 14, 2004
    Publication date: December 9, 2004
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Publication number: 20030067067
    Abstract: Arrangements are provided to effectively prevent wire disconnection generated due to an increase of heat applied to a semiconductor integrated circuit device The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 &mgr;m is provided in the connecting member.
    Type: Application
    Filed: November 18, 2002
    Publication date: April 10, 2003
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Publication number: 20010018264
    Abstract: The invention provides means for effectively preventing a wire disconnection generated due to an increase of calorie applied to a semiconductor integrated circuit device. The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 &mgr;m is provided in the connecting member.
    Type: Application
    Filed: May 9, 2001
    Publication date: August 30, 2001
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Publication number: 20010015481
    Abstract: The invention provides means for effectively preventing a wire disconnection generated due to an increase of calorie applied to a semiconductor integrated circuit device. The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 &mgr;m is provided in the connecting member.
    Type: Application
    Filed: February 20, 2001
    Publication date: August 23, 2001
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Patent number: 5031821
    Abstract: The present invention is characterized in that, in a ball wedge bonding using a fine bonding wire precoated with a thin insulating layer, ultrasonic vibration is applied to a capillary to effect the delivery of the wire smoothly during movement of the capillary to a second bonding point while delivering the wire after ball bonding at a first bonding point.
    Type: Grant
    Filed: August 16, 1989
    Date of Patent: July 16, 1991
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd., Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Tsuyoshi Kaneda, Susumu Okikawa, Hiroshi Mikino, Hiroshi Watanabe, Toshihiro Satou, Atsushi Onodera, Michio Tanimoto
  • Patent number: 4634270
    Abstract: A protective cover for photoprinting system comprises a cover portion made of a transparent thin plate of inorganic material, an antireflection multiple coating provided on at least one of the inner and outer surfaces of the cover plate, and a spacer arranged on the peripheral portion of the cover plate for keeping the inner surface of the cover plate away from the surface to be protected, e.g., pattern surface of photomask and sealing the space between them.Since the cover plate is made of inorganic material, the mechanical strength thereof is large. Since the cover plate is thin and the antireflection multiple coating is provided on the cover plate, absorption of light therein is little and confusion of the pattern image due to rays reflected by the boundaries of the cover plate is ignorable.
    Type: Grant
    Filed: October 18, 1985
    Date of Patent: January 6, 1987
    Assignees: Nippon Sheet Glass Co., Ltd., Hitachi Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Sadao Yokoo, Tadashi Shimomura, Soichi Torisawa, Masahiro Dan, Tsuyoshi Kaneda