Patents by Inventor Tsuyoshi Kanki
Tsuyoshi Kanki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10595412Abstract: A semiconductor device includes a printed circuit board that includes a first electrode, a resin substrate that includes a first face directed toward the printed circuit board, a second electrode formed in a second portion surrounding a first portion of the first face, a second face opposite the first face, and a third electrode formed in a third portion of the second face, the third portion overlapping the first portion in a plan view, a semiconductor chip that includes a coupling terminal joined to the third electrode, a conductive member that is formed between the printed circuit board and the resin substrate and contains a conductive particle and resin, and a solder bump that is formed between the printed circuit board and the resin substrate and is joined to the first electrode and the second electrode.Type: GrantFiled: August 14, 2017Date of Patent: March 17, 2020Assignee: FUJITSU LIMITEDInventors: Shinya Sasaki, Tsuyoshi Kanki
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Patent number: 10283446Abstract: A wiring board includes a base board and a plurality of wiring layers formed of a resin insulating film on the base board, wherein at least one of the wiring layers includes a fine wiring, a barrier film, which is not in contact with the fine wiring, is formed at a more outer side from the base board than the wiring layer including the fine wiring, and different types of resin insulating films are used for a wiring layer at an inner side of the barrier film close to the base board and a wiring layer at an outer side of the barrier film, respectively.Type: GrantFiled: May 1, 2017Date of Patent: May 7, 2019Assignee: FUJITSU LIMITEDInventors: Junya Ikeda, Tsuyoshi Kanki
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Publication number: 20180063960Abstract: A semiconductor device includes a printed circuit board that includes a first electrode, a resin substrate that includes a first face directed toward the printed circuit board, a second electrode formed in a second portion surrounding a first portion of the first face, a second face opposite the first face, and a third electrode formed in a third portion of the second face, the third portion overlapping the first portion in a plan view, a semiconductor chip that includes a coupling terminal joined to the third electrode, a conductive member that is formed between the printed circuit board and the resin substrate and contains a conductive particle and resin, and a solder bump that is formed between the printed circuit board and the resin substrate and is joined to the first electrode and the second electrode.Type: ApplicationFiled: August 14, 2017Publication date: March 1, 2018Applicant: FUJITSU LIMITEDInventors: Shinya Sasaki, Tsuyoshi Kanki
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Publication number: 20170352614Abstract: A wiring board includes a base board and a plurality of wiring layers formed of a resin insulating film on the base board, wherein at least one of the wiring layers includes a fine wiring, a barrier film, which is not in contact with the fine wiring, is formed at a more outer side than the base board than the wiring layer including the fine wiring, and different types of resin insulating films are used for a wiring layer at an inner side of the barrier film close to the base board and a wiring layer at an outer side of the barrier film, respectively.Type: ApplicationFiled: May 1, 2017Publication date: December 7, 2017Applicant: FUJITSU LIMITEDInventors: JUNYA IKEDA, Tsuyoshi Kanki
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Publication number: 20170110369Abstract: An electronic device includes: a first insulating film; an interconnection trench on a surface of the first insulating film; an interconnection pattern composed of Cu, the interconnection trench being filled with the interconnection pattern; a metal film on a surface of the interconnection pattern, the metal film having a higher elastic modulus than Cu; a second insulating film on the first insulating film; and a via plug composed of Cu and arranged in the second insulating film, the via plug being in contact with the metal film.Type: ApplicationFiled: December 28, 2016Publication date: April 20, 2017Applicant: FUJITSU LIMITEDInventors: Tsuyoshi KANKI, Hideki KITADA
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Publication number: 20160381795Abstract: An electronic device includes: a substrate; a Cu-containing wiring layer formed over the substrate; a barrier metal layer that covers a surface of the Cu-containing wiring layer and suppresses diffusion of Cu; and a coating insulating layer that covers the barrier metal layer, wherein the barrier metal layer has a void that does not reach the Cu-containing wiring layer, and the void is filled with the coating insulating layer.Type: ApplicationFiled: May 23, 2016Publication date: December 29, 2016Applicant: FUJITSU LIMITEDInventors: Junya Ikeda, Miwa Kozawa, Tsuyoshi Kanki, Yoshihiro Nakata
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Patent number: 9263326Abstract: After a copper interconnection is formed above a substrate, a surface of the copper interconnection is activated by performing acid cleaning. Thereafter, the substrate is immersed in a BTA (Benzo triazole) aqueous solution to form a protection film covering the surface of the copper interconnection. At this time, Cu—N—R bonds (R is an organic group) are formed in grain boundary portions in the surface of the copper interconnection. Thereafter, the protection film is removed by performing alkaline cleaning. The Cu—N—R bonds remain in the grain boundary portions in the surface of the copper interconnection even after the protection film is removed. Subsequently, the surface of the copper interconnection is subjected to an activation process, and a barrier layer is formed thereafter by electroless-plating the surface of the copper interconnection with NiP or CoWP.Type: GrantFiled: May 7, 2015Date of Patent: February 16, 2016Assignee: FUJITSU LIMITEDInventors: Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi
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Patent number: 9196526Abstract: A semiconductor device includes a copper interconnect provided in a trench in an insulation film, a metal film provided on the insulation film along a boundary between the insulation film and the copper interconnect, a barrier metal provided between an inner wall of the trench and the copper interconnect and extending over the metal layer, a first metal cap to cover the copper interconnect and the barrier metal located over the metal film, and a second metal cap to continuously cover the first metal cap, the barrier metal and the metal film.Type: GrantFiled: November 12, 2013Date of Patent: November 24, 2015Assignee: FUJITSU LIMITEDInventor: Tsuyoshi Kanki
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Publication number: 20150243555Abstract: After a copper interconnection is formed above a substrate, a surface of the copper interconnection is activated by performing acid cleaning. Thereafter, the substrate is immersed in a BTA (Benzo triazole) aqueous solution to form a protection film covering the surface of the copper interconnection. At this time, Cu—N—R bonds (R is an organic group) are formed in grain boundary portions in the surface of the copper interconnection. Thereafter, the protection film is removed by performing alkaline cleaning. The Cu—N—R bonds remain in the grain boundary portions in the surface of the copper interconnection even after the protection film is removed. Subsequently, the surface of the copper interconnection is subjected to an activation process, and a barrier layer is formed thereafter by electroless-plating the surface of the copper interconnection with NiP or CoWP.Type: ApplicationFiled: May 7, 2015Publication date: August 27, 2015Inventors: Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi
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Patent number: 8872040Abstract: A wiring structure includes: an insulating film formed over a substrate; a plurality of wirings formed on the insulating film; and an inducing layer, which is formed on the insulating film in a region between the plurality of wirings, a constituent atoms of the wirings are diffused in the inducing layer.Type: GrantFiled: June 22, 2012Date of Patent: October 28, 2014Assignee: Fujitsu LimitedInventors: Tsuyoshi Kanki, Shoichi Suda, Yoshihiro Nakata
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Publication number: 20140264875Abstract: A semiconductor device includes a copper interconnect provided in a trench in an insulation film, a metal film provided on the insulation film along a boundary between the insulation film and the copper interconnect, a barrier metal provided between an inner wall of the trench and the copper interconnect and extending over the metal layer, a first metal cap to cover the copper interconnect and the barrier metal located over the metal film, and a second metal cap to continuously cover the first metal cap, the barrier metal and the metal film.Type: ApplicationFiled: November 12, 2013Publication date: September 18, 2014Applicant: FUJITSU LIMITEDInventor: Tsuyoshi KANKI
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Patent number: 8791561Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.Type: GrantFiled: February 11, 2013Date of Patent: July 29, 2014Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa
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Patent number: 8691699Abstract: A manufacturing method of a semiconductor device includes: forming an insulating layer above a substrate; forming a recessed section in the insulating layer; forming, on the insulating layer, a mask pattern having a first opening which exposes the recessed section, and a second opening which is arranged outside the first opening and does not expose the recessed section; forming a first conductive member and a second conductive member by respectively depositing a conductive material in the first opening and the second opening; and polishing and removing the first conductive member and the second conductive member on the upper side of the insulating layer so as to leave the first conductive member in the recessed section.Type: GrantFiled: March 22, 2012Date of Patent: April 8, 2014Assignee: Fujitsu LimitedInventors: Tsuyoshi Kanki, Shoichi Suda, Shinya Sasaki
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Publication number: 20130093092Abstract: An electronic device includes: a first insulating film; an interconnection trench on a surface of the first insulating film; an interconnection pattern composed of Cu, the interconnection trench being filled with the interconnection pattern; a metal film on a surface of the interconnection pattern, the metal film having a higher elastic modulus than Cu; a second insulating film on the first insulating film; and a via plug composed of Cu and arranged in the second insulating film, the via plug being in contact with the metal film.Type: ApplicationFiled: September 13, 2012Publication date: April 18, 2013Applicant: FUJITSU LIMITEDInventors: Tsuyoshi Kanki, Hideki Kitada
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Patent number: 8399295Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.Type: GrantFiled: February 2, 2011Date of Patent: March 19, 2013Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa
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Publication number: 20130048358Abstract: A wiring structure includes: an insulating film formed over a substrate; a plurality of wirings formed on the insulating film; and an inducing layer, which is formed on the insulating film in a region between the plurality of wirings, a constituent atoms of the wirings are diffused in the inducing layer.Type: ApplicationFiled: June 22, 2012Publication date: February 28, 2013Applicant: FUJITSU LIMITEDInventors: Tsuyoshi KANKI, Shoichi Suda, Yoshihiro Nakata
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Publication number: 20120273964Abstract: A manufacturing method of a semiconductor device includes: forming an insulating layer above a substrate; forming a recessed section in the insulating layer; forming, on the insulating layer, a mask pattern having a first opening which exposes the recessed section, and a second opening which is arranged outside the first opening and does not expose the recessed section; forming a first conductive member and a second conductive member by respectively depositing a conductive material in the first opening and the second opening; and polishing and removing the first conductive member and the second conductive member on the upper side of the insulating layer so as to leave the first conductive member in the recessed section.Type: ApplicationFiled: March 22, 2012Publication date: November 1, 2012Applicant: Fujitsu LimitedInventors: Tsuyoshi KANKI, Shoichi Suda, Shinya Sasaki
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Publication number: 20120181070Abstract: After a copper interconnection is formed above a substrate, a surface of the copper interconnection is activated by performing acid cleaning. Thereafter, the substrate is immersed in a BTA (Benzo triazole) aqueous solution to form a protection film covering the surface of the copper interconnection. At this time, Cu—N—R bonds (R is an organic group) are formed in grain boundary portions in the surface of the copper interconnection. Thereafter, the protection film is removed by performing alkaline cleaning. The Cu—N—R bonds remain in the grain boundary portions in the surface of the copper interconnection even after the protection film is removed. Subsequently, the surface of the copper interconnection is subjected to an activation process, and a barrier layer is formed thereafter by electroless-plating the surface of the copper interconnection with NiP or CoWP.Type: ApplicationFiled: March 27, 2012Publication date: July 19, 2012Applicant: FUJITSU LIMITEDInventors: Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi
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Patent number: 8101513Abstract: (a) A recess is formed through an insulating film formed over a semiconductor substrate. (b) After the recess is formed, a temperature of the substrate is raised to 300° C. or higher at a temperature rising rate of 10° C./s or slower and a first degassing process is executed. (c) After the first degassing process, a conductive film is deposited on the insulating film, the conductive film being embedded in the recess. (d) The deposited conductive film is polished until the insulating film is exposed. It is possible to suppress occurrence of defects during CMP to be performed after a conductive member is deposited on the surface of the insulating film having a recess formed therethrough.Type: GrantFiled: March 3, 2006Date of Patent: January 24, 2012Assignee: Fujitsu LimitedInventors: Tsuyoshi Kanki, Nobuyuki Ohtsuka, Hisaya Sakai, Noriyoshi Shimizu
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Publication number: 20110187002Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.Type: ApplicationFiled: February 2, 2011Publication date: August 4, 2011Applicants: FUJITSU LIMITED, SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa