Patents by Inventor Tsuyoshi Koyashiki

Tsuyoshi Koyashiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8514638
    Abstract: In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage.
    Type: Grant
    Filed: December 11, 2011
    Date of Patent: August 20, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tsuyoshi Koyashiki, Jun Nagayama, Masahito Isoda, Tomoharu Awaya
  • Publication number: 20120213014
    Abstract: In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage.
    Type: Application
    Filed: December 11, 2011
    Publication date: August 23, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tsuyoshi KOYASHIKI, Jun Nagayama, Masahito Isoda, Tomoharu Awaya
  • Publication number: 20100133659
    Abstract: A semiconductor device including a plurality of circuit regions formed in a semiconductor substrate and a scribe region formed around the circuit regions for separating the respective circuit regions, the scribe region having a plurality of laminated interlayer films including a plurality of metal films and an optically-transparent insulation film formed between and on the plurality of metal films, wherein a first metal film included in a first upper interlayer film of the plurality of interlayer films is positionally offset in a vertical direction to a second metal film included in a second lower interlayer film under the first interlayer film.
    Type: Application
    Filed: October 14, 2009
    Publication date: June 3, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Akio Hara, Toyoji Sawada, Tsuyoshi Koyashiki, Hironori Fukaya
  • Patent number: 7375423
    Abstract: A semiconductor device includes a pad composed of plural wiring layers and a power supply ring to provide a power supply provided through the pad for the power supply to an internal circuit, and the pad for the power supply and the power supply ring are connected by vias provided respectively above and below the power supply ring. Consequently, even if the width of the pad is narrowed, the number of vias disposed to connect the pad for the power supply and the power supply ring can be at least doubled compared to the conventional one to increase the amount of a current which can be provided to the power supply ring, which makes it possible to provide the sufficient current from outside to the power supply ring even in the semiconductor device with the narrow-width pad.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: May 20, 2008
    Assignee: Fujitsu Limited
    Inventors: Takanori Watanabe, Tsuyoshi Koyashiki, Hiroyuki Ozawa, Chiaki Mimura
  • Publication number: 20060175698
    Abstract: A semiconductor device includes a pad composed of plural wiring layers and a power supply ring to provide a power supply provided through the pad for the power supply to an internal circuit, and the pad for the power supply and the power supply ring are connected by vias provided respectively above and below the power supply ring. Consequently, even if the width of the pad is narrowed, the number of vias disposed to connect the pad for the power supply and the power supply ring can be at least doubled compared to the conventional one to increase the amount of a current which can be provided to the power supply ring, which makes it possible to provide the sufficient current from outside to the power supply ring even in the semiconductor device with the narrow-width pad.
    Type: Application
    Filed: July 19, 2005
    Publication date: August 10, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Takanori Watanabe, Tsuyoshi Koyashiki, Hiroyuki Ozawa, Chiaki Mimura
  • Patent number: 5684423
    Abstract: A variable delay circuit which includes a first power source line for supplying a first power source voltage, a second power source line for supplying a second power source voltage which is smaller than the first power source voltage, an input terminal for receiving an input signal, a selection terminal for receiving a selection signal, an output terminal for outputting an output signal which is delayed relative to the input signal, a pull-up circuit coupled between the first power source line and the output terminal for carrying out a pull-up operation based on the input signal which is received via the input terminal, and a pull-down circuit coupled between the output terminal and the second power source line for carrying out a pull-down operation based on the input signal which is received via the input terminal. The pull-up or pull-down circuit has a delay time which is variable in response to the selection signal which is received via the selection terminal.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: November 4, 1997
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Koyashiki, Kohei Teruyama